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october 2008 rev 2 1/139 1 st7liteu05 st7liteu09 8-bit mcu with single voltage flash memory, adc, timers features memories ? 2k bytes single voltage flash program memory with readout pr otection, in-circuit and in-application programming (icp and iap). 10k write/erase cycles guaranteed, data retention: 20 years at 55 c ? 128 bytes ram ? 128 bytes data eeprom. 300k write/erase cycles guaranteed, data retention: 20 years at 55 c clock, reset and supply management ? 3-level low voltage supervisor (lvd) and auxiliary voltage detect or (avd) for safe power- on/off procedures ? clock sources: internal trimmable 8-mhz rc oscillator, internal low power, low frequency rc oscillator or external clock ? five power saving modes: halt, auto- wakeup from halt, active-halt, wait and slow interrupt management ? 11 interrupt vectors plus trap and reset ? 5 external interrupt lines (on 5 vectors) i/o ports ? 5 multifunctional bidirectional i/o lines ? 1 additional output line ? 6 alternate function lines ? 5 high sink outputs 2 timers ? one 8-bit lite timer (lt) with prescaler including: watchdog, 1 realtime base and 1 input capture ? one 12-bit auto-reload timer (at) with output compare function and pwm a/d converter ? 10-bit resolution for 0 to v dd ? 5 input channels instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode detection ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/software development package ? debug module dip8 so8 150? dfn8 table 1. device summary features st7ultralite st7liteu05 st7liteu09 program memory - bytes 2k ram (stack) - bytes 128 (64) eeprom -bytes - 128 peripherals lt timer w/ wdg, at timer w/ 1 pwm, 10-bit adc operating supply 2.4 v to 3.3 v @f cpu = 4 mhz, 3.3 v to 5.5 v @f cpu = 8 mhz cpu frequency up to 8 mhz rc operating temperature -40 c to +125 c packages so8 150?, dip8, dfn8, dip16 (1) 1. for development or tool prototyping purpos es only. not orderable in production quantities. www.st.com
contents st7liteu05 st7liteu09 2/139 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.1 in-circuit programming (icp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.2 in application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.1 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.2 flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7.1 flash control/status register (fcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 read operation (e2lat=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.2 write operation (e2lat=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.2 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 data eeprom readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
st7liteu05 st7liteu09 contents 3/139 5.7.1 eeprom control/status regi ster (eecsr) . . . . . . . . . . . . . . . . . . . . . . 26 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.2 index registers (x and y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.3 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3.4 condition code register (cc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3.5 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.1 main clock control/status register (mccsr) . . . . . . . . . . . . . . . . . . . . . 35 7.3.2 rc control register (rccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3.3 system integrity (si) control/status register (sicsr) . . . . . . . . . . . . . . . 36 7.3.4 avd threshold selection register (avdthcr) . . . . . . . . . . . . . . . . . . . . 36 7.3.5 clock controller control/status register (ckcntcsr) . . . . . . . . . . . . . . 37 7.4 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4.2 asynchronous external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4.3 external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4.4 internal low voltage detector (lvd) reset . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4.5 internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5.1 multiplexed io reset control register 1 (muxcr1) . . . . . . . . . . . . . . . . . 41 7.5.2 multiplexed io reset control register 0 (muxcr0) . . . . . . . . . . . . . . . . . 41 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 priority management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 interrupts and low power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
contents st7liteu05 st7liteu09 4/139 8.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3.1 external interrupt control register 1 (eicr1) . . . . . . . . . . . . . . . . . . . . . 45 8.3.2 external interrupt control register 2 (eicr2) . . . . . . . . . . . . . . . . . . . . . 45 8.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4.2 auxiliary voltage detector (avd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.4.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.4.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4.1 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.5 auto-wakeup from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.5.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2.1 input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2.2 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.2.4 analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.6 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.1 lite timer (lt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
st7liteu05 st7liteu09 contents 5/139 11.1.4 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.1.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2 12-bit autoreload timer (at) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.2.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11.3 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 11.3.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.3.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.1.1 inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.1.4 indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.1.5 indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1.6 indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1.7 relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2.1 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
contents st7liteu05 st7liteu09 6/139 13.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 13.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 13.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . 98 13.3.3 auxiliary voltage detector (avd) thresholds . . . . . . . . . . . . . . . . . . . . . . 98 13.3.4 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.4.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.4.2 internal rc oscillator supply characteristics . . . . . . . . . . . . . . . . . . . . 102 13.4.3 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 13.7.1 functional ems (electro magnetic susceptibility) . . . . . . . . . . . . . . . . 107 13.7.2 emi (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.8.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 13.8.2 output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.9.1 asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.10 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 127 15.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.1.1 option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.1.2 option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 15.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.3.1 starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.3.2 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.3.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
st7liteu05 st7liteu09 contents 7/139 15.3.4 order codes for development and programming tools . . . . . . . . . . . . . 132 15.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
list of tables st7liteu05 st7liteu09 8/139 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. data eeprom register map and re set values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. predefined rc oscillator ca libration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6. internal rc prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7. clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 table 8. cpu clock cycle delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. multiplexed io register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11. interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12. description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 13. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 14. avd threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 15. system integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 16. enabling/disabling active-halt and halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 17. configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 18. awu register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 table 19. dr value and output pin status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 20. i/o port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 21. i/o port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 22. effect of low power modes on i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 table 23. description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 24. port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 25. i/o port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 26. description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 27. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 28. lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 29. description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 30. interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 31. counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 32. register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 33. effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 34. channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 35. configuring the adc clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 36. adc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 37. description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 38. st7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 39. instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 40. instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 89 table 41. instructions supporting direct, indexed, indi rect and indirect indexed addressing modes . 90 table 42. instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 43. st7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 44. illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 45. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 46. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 47. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 48. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
st7liteu05 st7liteu09 list of tables 9/139 table 49. operating characteristics with lvd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 50. operating characteristics with avd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 51. voltage drop between avd flag set and lvd reset generation . . . . . . . . . . . . . . . . . . . . . 99 table 52. internal rc oscillator characteri stics (5.0 v calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 53. internal rc oscillator characteristics (3.3 v calibra tion) . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 54. supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 56. on-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 57. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 58. auto-wakeup rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 59. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 60. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 61. eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 62. ems test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 63. emi emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 64. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 table 65. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 66. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 67. output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 68. asynchronous reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 69. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 70. adc accuracy with vdd = 3.3 v to 5.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 71. adc accuracy with vdd = 2.7 v to 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 72. adc accuracy with vdd = 2.4 v to 2.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 73. 8-lead very thin fine pitch dual flat no-lead package, mechanical data . . . . . . . . . . . . . . 122 table 74. 8-pin plastic small outline package - 150-mil width, mechanical data. . . . . . . . . . . . . . . . 123 table 75. 8-pin plastic dual in-line outline package, 3 00-mil width, mechanical data. . . . . . . . . . . . 124 table 76. 16-pin plastic dual in-line package, 300-mil width, mechanical data . . . . . . . . . . . . . . . . 125 table 77. package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 78. startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 79. lvd threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 80. sector 0 size selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 81. development tool order codes for the st7liteu0x family. . . . . . . . . . . . . . . . . . . . . . . . 133 table 82. st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 83. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
list of figures st7liteu05 st7liteu09 10/139 list of figures figure 1. general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. 8-pin so and dip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. 8-pin dfn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. 16-pin package pinout 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. eeprom block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. data eeprom programmin g flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. data eeprom write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. data eeprom programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 figure 15. reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17. reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 20. reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 21. using the avd to monitor vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 22. power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 23. slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 26. active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 27. halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 28. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29. awufh mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 30. awuf halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 31. awufh mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 32. i/o port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 33. interrupt i/o port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 34. lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 35. watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 36. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 37. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 38. pwm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 39. pwm signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 40. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 41. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 42. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 43. fcpu maximum operating frequency versus v dd supply voltage . . . . . . . . . . . . . . . . . . . 97 figure 44. typical accuracy with rccr=rccr0 vs vdd= 2.4-6.0 v and te mperature . . . . . . . . . . 100 figure 45. typical accuracy with rccr=rccr1 vs vdd= 2.4-6.0v and te mperature. . . . . . . . . . . 100 figure 46. typical idd in run mode vs. internal clock frequency and vdd . . . . . . . . . . . . . . . . . . . 103 figure 47. typical idd in wfi mode vs. internal clock frequency and vdd . . . . . . . . . . . . . . . . . . . 103 figure 48. typical idd in slow, slow-wait and active-halt mode vs vdd & int
st7liteu05 st7liteu 09 list of figures 11/139 rc = 8 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 49. idd vs temp @vdd 5 v & int rc = 8 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 50. idd vs temp @vdd 5 v & int rc = 4 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 51. idd vs temp @vdd 5v & int rc = 2 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 52. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 53. typical ipu vs. vdd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 figure 54. typical rpu vs. vdd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 55. typical vol at vdd = 2.4 v (standard pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 56. typical vol at vdd = 3 v (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 57. typical vol at vdd = 5 v (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 58. typical vol at vdd = 2.4 v (hs pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 59. typical vol at vdd = 3 v (hs pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 figure 60. typical vol at vdd = 5 v (hs pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 figure 61. typical vdd-voh at vdd = 2.4 v (hs pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 62. typical vdd-voh at vdd = 3 v (hs pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 63. typical vdd-voh at vdd = 5 v (hs pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 64. typical vol vs. vdd (hs pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 65. typical vdd-voh vs. vdd (hs pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 66. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 67. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 68. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 69. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 70. 8-lead very thin fine pitch dual flat no-lead package, package outline . . . . . . . . . . . . . . . 121 figure 71. 8-pin plastic small outline package - 150-mil width, package outline . . . . . . . . . . . . . . . . 122 figure 72. 8-pin plastic dual in-line outline package - 300-mil width, package outline. . . . . . . . . . . . 123 figure 73. 16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 125 figure 74. st7liteu0 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
introduction st7liteu05 st7liteu09 12/139 1 introduction the st7ultralite is a member of the st7 microcontroller family. all st7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. the st7ultralite features flash memory with byte-by-byte in-circuit programming (icp) and in-application prog ramming (iap) capability. under software control, the st7ultralite device can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling th e design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 13 on page 95 . the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. figure 1. general block diagram 8-bit core alu address and data bus pa3 / reset port a 10-bit adc with watchdog internal clock control ram (128 bytes) pa5:0 (6 bits) v ss v dd power supply 8-mhz rc osc. lite timer memory 12-bit auto- reload timer flash 2 kbyte lvd awu rc osc. external clock data eeprom (128 bytes)
st7liteu05 st7liteu09 pin description 13/139 2 pin description figure 2. 8-pin so and dip package pinout 1. hs : high sink capability 2. eix : associated external interrupt vector figure 3. 8-pin dfn package pinout 1. hs : high sink capability 2. eix : associated external interrupt vector v dd pa5 (hs) / ain4 / clkin pa 3 / r e s e t v ss pa0 (hs) / ain0 / atpwm / iccdata pa 2 (hs) / ltic / ain2 pa1 (hs) / ain1 / iccclk pa4 (hs) / ain3 / mco 1 2 3 4 8 7 6 5 ei4 ei3 ei2 ei1 ei0 v dd pa5 (hs) / ain4 / clkin pa3 / reset v ss pa0 (hs) / ain0 / atpwm / iccdata pa 2 (hs) / ltic / ain2 pa1 (hs) / ain1 / iccclk pa4 (hs) / ain3 / mco 1 2 3 4 8 7 6 5 ei4 ei3 ei2 ei1 ei0
pin description st7liteu05 st7liteu09 14/139 figure 4. 16-pin package pinout 1) 1. for development or tool prototyping purposes only. package not orderable in production quantities. 2. must be tied to ground note: the differences versus the 8-pin packages are listed below: the icc signals (iccclk and iccdata) are mapped on dedicated pins; the reset signal is mapped on a dedicated pin. it is not multiplexed with pa3. pa3 pin is always configured as output. any change on multiplexed io reset control registers (muxcr1 and muxcr2) will have no effect on pa3 functionality. refer to ?register description? on page 41. reserved 2) v dd iccclk nc v ss pa1 (hs) / ain1 pa0 (hs) / ain0 / atpwm reset 1 2 3 4 1 1 1 1 ei4 ei3 ei1 ei0 pa5 (hs) / ain4 / clkin pa4 (hs) / ain3 / mco nc nc iccdata nc pa 2 (hs) / ltic / ain2 pa 3 5 7 6 8 12 11 10 9 ei2
st7liteu05 st7liteu09 pin description 15/139 legend / abbreviations for ta bl e 2 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3 v dd /0.7 v dd with input trigger output level: hs = high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog output: od = open drain, pp = push-pull the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 2. device pin description pin no. pin name type level port / control main function (after reset) alternate function input output input output float wpu int ana od pp 1v dd (1) s main power supply 2 pa5/ain4/clkin i/o c t hs x ei4 x x x port a5 analog input 4 or external clock input 3 pa4/ain3/mco i/o c t hs x ei3 x x x port a4 analog input 3 or main clock output 4 pa3/reset (2) o x xxport a3reset (2) 5 pa2/ain2/ltic i/o c t hs x ei2 x x x port a2 analog input 2 or lite timer input capture 6 pa1/ain1/iccclk i/o c t hs x ei1 xxxport a1 analog input 1 or in circuit communication clock caution: during normal operation this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in pull-up 7 pa 0 / a i n 0 / at p w m / iccdata i/o c t hs x ei0 x x x port a0 analog input 0 or auto-reload timer pwm or in circuit communication data 8v ss (1) s ground 1. it is mandatory to connect all available v dd and v dda pins to the supply voltage and all v ss and v ssa pins to ground. 2. after a reset, the multiplexed pa3/reset pin will act as reset . to configure this pin as output (port a3), write 55h to muxcr0 and aah to muxcr1. for further details, please refer to section 7.5 on page 41 .
register & memory map st7liteu05 st7liteu09 16/139 3 register & memory map as shown in figure 5 , the mcu is capable of addressing 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 128 bytes of ram and 1 kbyte of user program memory. the ram space includes up to 64 bytes for the stack from 00c0h to 00ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see figure 5 ) mapped in the upper part of the st7 addressing space so the reset and interrupt ve ctors are located in sector 0 (fc00-ffffh). the size of flash sector 0 and other device options are configurable by option byte. important: memory locations marked as ?reserved? must never be accessed. accessing a reseved area can have unpredictable effects on the device. figure 5. memory map 1. see section 7.2 on page 32 . note: dee0h, dee1h, dee2h and dee3h addresses are located in a reserved area but are special bytes containing also the rc calibration values which are read-accessible only in user mode. if all the eeprom data or flash space (including the rc calibration values locations) has been erased (after the readout protection removal), then the rc calibration values can still be obtain ed through thes e addresses. 0000h ram flash memory (2k) interrupt & reset vectors hw registers 0080h 007fh (see ta b l e ) ffe0h ffffh (see ta bl e 1 0 ) 0100h 00ffh short addressing ram (zero page) 64-byte stack 00ffh 0080h 00c0h (128 bytes) f800h f7ffh reserved ffdfh 1 kbyte 1 kbyte sector 1 sector 0 2k flash ffffh fc00h fbffh f800h program memory dee0h 1) rccrh0 rccrl0 dee1h rccrh1 rccrl1 dee2h dee3h data eeprom 1080h 107fh 1000h 0fffh reserved (128 bytes)
st7liteu05 st7liteu09 register & memory map 17/139 table 3. hardware register map address block register label register name reset status (1) remarks (1) 0000h 0001h 0002h port a pa d r paddr pao r port a data register port a data direction register port a option register 00h (2) 08h 02h (3) r/w r/w r/w 0003h to 000ah reserved area (8 bytes) 000bh 000ch lite timer lt c s r lt i c r lite timer control/status register lite timer input capture register 0xh 00h r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h auto-reload timer at c s r cntrh cntrl at r h at r l pwmcr pwm0csr timer control/status register counter register high counter register low auto-reload register high auto-reload register low pwm output control register pwm 0 control/status register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 0014h to 0016h reserved area (3 bytes) 0017h 0018h auto-reload timer dcr0h dcr0l pwm 0 duty cycle register high pwm 0 duty cycle register low 00h 00h r/w r/w 0019h to 002eh reserved area (22 bytes) 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom control/status register 00h r/w 0031h to 0033h reserved area (3 bytes) 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d data register low 00h xxh 00h r/w read only r/w 0037h itc eicr1 external interrupt control register 1 00h r/w 0038h mcc mccsr main clock control/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator control register system integrity cont rol/status register ffh 0000 0x00b r/w r/w 003bh to 003ch reserved area (2 bytes) 003dh itc eicr2 external interrupt control register 2 00h r/w 003eh avd avdthcr avd threshold selection register 03h r/w 003fh clock controller ckcntcsr clock controller control/status register 09h r/w 0040h to 0046h reserved area (7 bytes) 0047h 0048h muxio- reset muxcr0 muxcr1 mux io-reset control register 0 mux io-reset control register 1 00h 00h r/w r/w
register & memory map st7liteu05 st7liteu09 18/139 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h dm (4) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w 0051h to 007fh reserved area (47 bytes) 1. legend: x=undefined, r/w=read/write 2. the contents of the i/o port dr registers are readable only in output conf iguration. in input confi guration, the values of th e i/o pins are returned instead of the dr register contents. 3. the bits associated with unavailable pi ns must always keep their reset value. 4. for a description of the dm registers, see the st7 icc protocol reference manual. table 3. hardware register map (continued) address block register label register name reset status (1) remarks (1)
st7liteu05 st7liteu09 flash program memory 19/139 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming or in-application programming. the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte readout and write protection 4.3 programming modes the st7 can be programmed in three different ways: insertion in a programming tool. in this mode, flash sectors 0 and 1 and option byte row can be programmed or erased. in-circuit programming. in this mode, flash sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. in-application programming. in this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit communication) which allows an st7 plugged on a printed circuit board (pcb) to communicate with an external programming device connected via cable. icp is performed in three steps: switch the st7 to icc mode (in-circuit communications). this is done by driving a specific signal sequ ence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific reset vector which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. download icp driver code in ram from the iccdata pin execute icp driver code in ram to program the flash memory
flash program memory st7liteu05 st7liteu09 20/139 depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in applicati on programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.4 icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin (see note 1) iccdata: icc input serial data pin clkin: main clock input for external source v dd : application board power supply (see note 3) figure 6. typical icc interface 1. if the iccclk or iccdata pins are only usedas output s in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an ic c session is not in progress, the iccclk and iccdata pins arenot available for the application. if they are used as inputs by the application, isolation such as a se rial resistor has to be implement ed in case another device forces the signal. refer to the programmingtool docum entation for recommended resistor values. 2. during the icp session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset circ uit if it drives more than 5 ma at high level (push pull output or pull-up resistor < 1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc netwo rk with r>1k or a reset management ic with open drain output and pull-up resistor >1 k, no additional components are needed. in all cases the user must icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) st7 clkin optional see note 1 see note 1 and caution see note 2 application reset source application i/o (see note 4) 3.3k (see note 5)
st7liteu05 st7liteu09 flash program memory 21/139 ensure that no external reset is generated by the application dur ing the icc session. 3. the use of pin 7 of the icc connector depends on t he programming tool architecture. this pin must be connected when using most st progr amming tools (it is used to moni tor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the clkin pin of t he st7 when icc mode is selected with option bytes disabled (35-pulse icc entry mode). when option bytes are enabled (38-pulse icc entry mode), the internal rc clock is forc ed, regardless of the selection in the option byte. 5. a serial resistor must be connected to icc connecto r pin 6 in order to prevent contention on pa3/reset pin. contention may occur if a tool forces a state on reset pin while pa3 pin forces the opposite state in output mode. the resistor value is defined to limit the current below 2 ma at 5 v. if pa3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the reset pin (pa3). to allow the programming tool to drive the reset pin below v il , special care must also be taken when a pull-up is placed on pa3 for application reasons. caution: during normal operation, iccclk pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up. 4.5 memory protection there are two different types of memory protection: readout protection and write/erase protection which can be applied individually. 4.5.1 readout protection readout protection, when selected provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. program memory is protected. in flash devices, this protection is removed by reprogramming the option. in this case, program memory is automatically erased, and the device can be reprogrammed. readout protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impossible to both overwrite and erase program memory. its purpose is to provide advanced security to applications and prevent any change being made to the memory content. warning: once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte.
flash program memory st7liteu05 st7liteu09 22/139 4.6 related documentation for details on flash programming and icc pr otocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . 4.7 register description 4.7.1 flash control/st atus register (fcsr) this register controls the xflash erasing and programming using icp, iap or other programming methods. 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) when an epb or another programm ing tool is used (in socket or icp mode), the rass keys are sent automatically. reset value: 000 0000 (00h) 7 0 00000optlatpgm read/write address (hex.) register label 76543210 002fh fcsr reset value - 0 - 0 - 0 - 0 - 0 opt 0 lat 0 pgm 0
st7liteu05 st7liteu09 data eeprom 23/139 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back-up for storing data. using the eeprom re quires a basic access pr otocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltag e (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management readout protection figure 7. eeprom block diagram 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eeprom control/status register (eecsr). the flowchart in figure 8 describes these different memory access modes. 5.3.1 read operation (e2lat=0) the eeprom can be read as a normal rom lo cation when the e2lat bit of the eecsr register is cleared. eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus
data eeprom st7liteu05 st7liteu09 24/139 on this device, data eeprom ca n also be used to execute ma chine code. take care not to write to the data eeprom while executing from it. this would result in an unexpected code being executed. 5.3.2 write operation (e2lat=1) to access the write mode, the e2lat bit has to be set by software (the e2pgm bit remains cleared). when a write access to the eeprom ar ea occurs, the value is latched inside the 32 data latches according to its address. when pgm bit is set by the software, all the prev ious bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is determined by the last eeprom write sequence. to avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note: care should be taken during the programming cycle. writing to the same memory location will over-program the memory (logical and between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of the e2lat bit. it is no t possible to read the latched data. this note is ilustrated by the figure 10 . figure 8. data eeprom programming flowchart read mode e2lat=0 e2pgm=0 write mode e2lat=1 e2pgm=0 read bytes in eeprom area write up to 32 bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat=1 e2pgm=1 (set by software) e2lat 01 cleared by hardware
st7liteu05 st7liteu09 data eeprom 25/139 figure 9. data eeprom write operation 1. if a programming cycle is interrupted (by a reset acti on), the integrity of the data in memory is not guaranteed. 5.4 power saving modes 5.4.1 wait mode the data eeprom can ent er wait mode on execution of the wfi instruction of the microcontroller or wh en the microcontroller enters acti ve-halt mode.the data eeprom will immediately enter this mode if there is no programming in progre ss, otherwise the data eeprom will finish the cycle an d then enter wait mode. 5.4.2 active-halt mode refer to wait mode. 5.4.3 halt mode the data eeprom immediately ent ers halt mode if the microcon troller execut es the halt instruction. therefore the eeprom will stop the function in progress, and data may be corrupted. 5.5 access error handling if a read access o ccurs while e2lat=1, then the data bus will not be driven. if a write access occurs while e2lat=0, th en the data on the bus will not be latched. if a programming cycle is interrupted (by a reset action), the integrity of the data in memory will not be guaranteed. byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row / byte ? 0123 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition
data eeprom st7liteu05 st7liteu09 26/139 5.6 data eeprom readout protection the readout protection is enabled through an option bit (see option byte section). when this option is selected, the programs and data stored in the eeprom memory are protected against readout (including a re-wri te protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire program memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 10. data eeprom programming cycle 5.7 register description 5.7.1 eeprom control/st atus register (eecsr) address: 0030h reset value: 0000 0000 (00h) bits 7:2 = reserved , forced by hardware to 0 bit 1 = e2lat latch access transfer bit: this bit is set by software. it is cleared by hardware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared 0: read mode 1: write mode bit 0 = e2pgm programming control and status bit this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note: if the e2pgm bit is cleared during the programming cycle, the memory data is not guaranteed. lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage 7 0 000000e2late2pgm read/write
st7liteu05 st7liteu09 data eeprom 27/139 table 4. data eeprom register map and reset values address (hex.) register label 76543210 0030h eecsr reset value 000000 e2lat 0 e2pgm 0
central processing unit st7liteu05 st7liteu09 28/139 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 6.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 6.3 cpu registers the six cpu registers shown in figure 11 are not present in the memory mapping and are accessed by specific instructions. 6.3.1 accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. 6.3.2 index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). 6.3.3 program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb).
st7liteu05 st7liteu09 central processing unit 29/139 figure 11. cpu registers 1. x = undefined value 6.3.4 condition code register (cc) the 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. reset value: 111x 1xxx these bits can be individually tested and/or controlled by specific instructions. bit 4 = h half carry bit this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. bit 3 = i interrupt mask bit this bit is set by hardware when entering in interrupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret instructions and is tested by the jrm and jrnm instructions. accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 1 1 x1 xx reset value = xxh reset value = xxh reset value = xxh 7 0 111hinzc read/write
central processing unit st7liteu05 st7liteu09 30/139 note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. bit 2 = n negative bit this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instructions. bit 1 = z zero bit this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow bit this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. 6.3.5 stack pointer (sp) reset value: 00 ffh the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 12 ). since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp5 to sp0 bits are set) which is the stack higher address. 15 8 00000000 read/write 7 0 1 1 sp5 sp4 sp3 sp2 sp1 sp0 read/write
st7liteu05 st7liteu09 central processing unit 31/139 the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 12 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. figure 12. stack manipulation example 1. stack higher address = 00ffh stack lower address = 00c0h pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 00ffh @ 00c0h
supply, reset and clock management st7liteu05 st7liteu09 32/139 7 supply, reset and clock management the device includes a range of utility featur es for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. 7.1 main features clock management ? 8 mhz internal rc oscillator (enabled by option byte) ? external clock input (enabled by option byte) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage detector (avd) with interr upt capability for mo nitoring the main supply 7.2 internal rc oscillator adjustment the st7 contains an internal rc oscillator with a specific accuracy for a given device, temperature and voltage. it ca n be selected as the start up clock through the cksel[1:0] option bits (see section 15.1 on page 127 ). it must be calibrated to obtain the frequency required in the application. this is done by software writing a 10-bit calibration value in the rccr (rc control register) and in the bits [6:5] in the sicsr (si control status register). whenever the microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be loaded in the rccr. predefined calibration values are stored in flash memory for 3.3 and 5 v v dd supply voltages at 25 c, as shown in the following table. table 5. predefined rc oscillator calibration values rccr conditions st7liteu05/st7liteu09 address rccrh0 v dd = 5 v t a = 25 c f rc = 8 mhz dee0h (1) (cr[9:2] bits) 1. dee0h, dee1h, dee2h and dee3h are located in a re served area but are special bytes containing also the rc calibration values which are r ead-accessible only in user mode. if all the flash space (including the rc calibration value locations) has been erased (afte r the readout protection removal), then the rc calibration values c an still be obtained through these two addresses. rccrl0 dee1h (1) (cr[1:0] bits) rccrh1 v dd = 3.3 v t a = 25 c f rc = 8 mhz dee2h (1) (cr[9:2] bits) rccrl1 dee3h (1) (cr[1:0] bits)
st7liteu05 st7liteu09 supply, reset and clock management 33/139 note: in icc mode, the internal rc oscillator is forced as a clock source, regardless of the selection in the option byte. refer to note 5 in section 4.4 on page 20 for further details. see ?electrical characteristics? on page 95. for more information on the frequency and accuracy of the rc oscillator. to improve clock stability and frequency accura cy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possible to the st7 device. caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an2326 for information on how to calibrate the rc frequency using an external reference signal. the st7ultralite also contains an auto wake up rc oscillator. this rc oscillator should be enabled to enter auto wake-up from halt mode. the auto-wakeup rc oscillator can also be co nfigured as the startup clock through the cksel[1:0] option bits (see section 15.1 on page 127 ). this is recommended for app lications where very low power consumption is required. switching from one startup clock to another can be done in run mode as follows (see figure 13 ): case 1: switching from internal rc to awu : 1. set the rc/awu bit in the ckcntcsr register to enable the awu rc oscillator 2. the rc_flag is cleared and the clock output is at 1. 3. wait 3 awu rc cycles till the awu_flag is set 4. the switch to the awu clock is made at the positive edge of the awu clock signal 5. once the switch is made, the internal rc is stopped case 2: switching from awu rc to internal rc: 1. reset the rc/awu bit to enable the internal rc oscillator 2. using a 4-bit counter, wait until 8 intern al rc cycles have elapsed. the counter is running on internal rc clock. 3. wait till the awu_flag is cleared (1aw u rc cycle) and the rc_flag is set (2 rc cycles) 4. the switch to the internal rc clock is made at the positive edge of the internal rc clock signal 5. once the switch is made, the awu rc is stopped note: 1 when the internal rc is not selected, it is stopped so as to save power consumption. 2 when the internal rc is selected, the awu rc is turned on by hardware when entering auto wake-up from halt mode. 3 when the external clock is selected , the awu rc oscillator is always on.
supply, reset and clock management st7liteu05 st7liteu09 34/139 figure 13. clock switching figure 14. clock management block diagram internal rc awu rc set rc/awu poll awu_flag until set internal rc reset rc/awu poll rc_flag until set awu rc mccsr sms peripherals (1ms timebase @ 8 mhz f osc ) f osc /32 f osc f osc f ltimer lite timer counter 13-bit f cpu to cpu and 0 1 cr6 cr9 cr2 cr3 cr4 cr5 cr8 cr7 rccr f osc clkin tunable oscillator internal rc option bits cksel[1:0] /2 divider awu 8 mhz 2 mhz 1 mhz 4 mhz prescaler rc 8 mhz(f rc ) 33khz clock controller ext clock awu ck rc osc cr1 cr0 sicsr /32 divider f clkin ckcntcsr rc/awu 500 khz mco mco avdthcr ck2 ck1 ck0
st7liteu05 st7liteu09 supply, reset and clock management 35/139 7.3 register description 7.3.1 main clock contro l/status register (mccsr) reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bit 1 = mco main clock out enable bit this bit is read/write by software and cleared by hardware after a reset. this bit allows to enable the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode selection bit this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc ) 1: slow mode (f cpu = f osc /32) 7.3.2 rc control register (rccr) reset value: 1111 1111 (ffh) bits 7:0 = cr[9:2] rc oscillator frequency adjustment bits these bits, as well as cr[1:0] bits in the sicsr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain the requ ired accuracy. the application can store the correct value for each voltage range in flash memory and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency note: to tune the oscillator, write a series of different values in the register un til the correct frequency is reached. the fastest method is to use a dichotomy starting with 80h. 7 0 000000mcosms read/write 7 0 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 read/write
supply, reset and clock management st7liteu05 st7liteu09 36/139 7.3.3 system integrity (si) con trol/status register (sicsr) reset value: 0000 0x00 (0xh) bit 7 = reserved, must be kept cleared. bits 6:5 = cr[1:0] rc oscillator frequency adjustment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain the requ ired accuracy. refer to section 7.2: internal rc os cillator adjustment on page 32 . bits 4:3 = reserved, must be kept cleared. bits 2:0 = system integrity bits. refer to section 8.4: system integrity management (si) on page 46 . 7.3.4 avd threshold selection register (avdthcr) reset value: 0000 0011 (03h) bits 7:5 = ck[2:0] internal rc prescaler selection these bits are set by software and cleared by hardware after a reset. these bits select the prescaler of the internal rc oscillator. see figure 14 on page 34 and the following table and note: note: if the internal rc is used with a supply operating range below 3.3v, a division ratio of at least 2 must be enabled in the rc prescaler. bits 4:2 = reserved, must be kept cleared. bits 1:0 = avd threshold selection bits. refer to section 8.4: system integrity management (si) on page 46 . 7 0 0 cr1 cr0 0 0 lvdrf avdf avdie read/write 7 0 ck2 ck1 ck0 0 0 0 avd1 avd0 read/write table 6. internal rc prescaler selection bits ck2 ck1 ck0 f osc 001 f rc/2 010 f rc/4 011 f rc/8 100 f rc/16 others f rc
st7liteu05 st7liteu09 supply, reset and clock management 37/139 7.3.5 clock controller control /status register (ckcntcsr) reset value: 0000 1001 (09h) bits 7:4 = reserved, must be kept cleared. bit 3 = awu_flag awu selection bit this bit is set and cleared by hardware. 0: no switch from awu to rc requested 1: awu clock activated and temporization completed bit 2 = rc_flag rc selection bit this bit is set and cleared by hardware. 0: no switch from rc to awu requested 1: rc clock activated and temporization completed bit 1 = reserved, must be kept cleared. bit 0 = rc/awu rc/awu selection bit 0: rc enabled 1: awu enabled (default value) 7 0 0000awu_flagrc_flag0rc/awu read/write table 7. clock register map and reset values address (hex.) register label 765 4 3 2 1 0 0038h mccsr reset value - 0 - 0 - 0 - 0 - 0 - 0 mco 0 sms 0 0039h rccr reset value cr9 1 cr8 1 cr7 1 cr6 1 cr5 1 cr4 1 cr3 1 cr2 1 003ah sicsr reset value - 0 cr1 0 cr0 0 - 0 - 0 lvdrf x avdf 0 avdie 0 003eh avdthcr reset value ck2 0 ck1 0 ck0 0 - 0 - 0 - 0 avd1 1 avd2 1 003fh ckcntcsr reset value - 0 - 0 - 0 - 0 awu_flag 1 rc_flag 0 - 0 rc/awu 1
supply, reset and clock management st7liteu05 st7liteu09 38/139 7.4 reset sequence manager (rsm) 7.4.1 introduction the reset sequence manager includes three reset sources as shown in figure 16 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to figure 16 . these sources act on the reset pin and it is always kept low during the delay phase. the reset service routine vector is fixed at addresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 15 : active phase depending on the reset source 256 or 512 cpu clock cycle delay (see table below) reset vector fetch caution: when the st7 is unprogrammed or fully erased, the flash is blank and the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 256 or 512 cpu clock cycle delay allows the oscillator to stab ilise and ensures that recovery has taken place from the reset state. the shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte after a reset or depending on the clock source selected before entering halt mode or awu from halt mode. refer to ta b l e 8 . the reset vector fetch phase duration is 2 clock cycles. figure 15. reset sequence phases table 8. cpu clock cycle delay clock source cpu clock cycle delay internal rc oscillator 512 external clock (connected to clkin pin) awurc 256 reset active phase internal reset 256 or 512 clock cycles fetch vector
st7liteu05 st7liteu09 supply, reset and clock management 39/139 figure 16. reset block diagram 1. see ?illegal opcode reset? on page 92. for mo re details on illegal opcode reset conditions. 7.4.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in accordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 17 ). this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous sign al which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 7.4.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specif ied for the selected f clkin frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc network connected to the reset pin. 7.4.4 internal low voltage detector (lvd) reset two different reset sequences caused by the internal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd supply, reset and clock management st7liteu05 st7liteu09 40/139 7.4.5 internal watchdog reset the reset sequence generated by a internal watchdog counter overflow is shown in figure 17 . starting from the watchdog co unter underflow, the device reset pin acts as an output that is pulled low during at least t w(rstl)out . figure 17. reset sequences v dd run reset pin external watchdog active phase v it+(lvd) v it-(lvd) t h(rstl)in run watchdog underflow t w(rstl)out run run reset reset source external reset lvd reset watchdog reset internal reset (256 or 512 t cpu ) vector fetch active phase active phase
st7liteu05 st7liteu09 supply, reset and clock management 41/139 7.5 register description 7.5.1 multiplexed io reset control register 1 (muxcr1) reset value: 0000 0000 (00h) 7.5.2 multiplexed io reset control register 0 (muxcr0) reset value: 0000 0000 (00h) bits 15:0 = mir[15:0] this 16-bit register is read/write by software but can be written only once between two reset events. it is cleared by hardware after a reset; when both muxcr0 and muxcr1 registers are at 00h, the mult iplexed pa3/reset pin will act as reset . to configure this pin as output (port a3), write 55h to muxcr0 and aah to muxcr1. these registers are one-time writable only. to configure pa3 as general purpose output: after power-on / reset, the application program has to configure the i/o port by writing to these registers as described above. once the pin is configured as an i/o output, it cannot be changed back to a reset pin by the application code. to configure pa3 as reset : an internally generated reset (such as po r, wdg, illegal opcode) will clear the two registers and the pin will act a gain as a reset function. ot herwise, a power-down is required to put the pin back in reset configuration. table 9. multiplexed io register map and reset values 7 0 mir15 mir14 mir13 mir12 mir11 mir10 mir9 mir8 read/write once only 7 0 mir7 mir6 mir5 mir4 mir3 mir2 mir1 mir0 read/write once only address (hex.) register label 76543210 0047h muxcr0 reset value mir7 0 mir6 0 mir5 0 mir4 0 mir3 0 mir2 0 mir1 0 mir0 0 0048h muxcr1 reset value mir15 0 mir14 0 mir13 0 mir12 0 mir11 0 mir10 0 mir9 0 mir8 0
interrupts st7liteu05 st7liteu09 42/139 8 interrupts the st7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the ?interrupt mapping? table and a non-maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 18 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent additional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector addresses). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit is cleared and the main program resumes. priority management by default, a servicing interrupt cannot be interrupted because the i bit is set by hardware entering in interrupt routine. in the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced firs t (see the interrupt mapping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifically mentioned interrupts allow the processor to leave th e halt low power mode (refer to the ?exit from halt? column in the interrupt mapping table). 8.1 non maskable software interrupt this interrupt is entered when the trap instruction is executed regardless of the state of the i bit. it is serviced according to the flowchart in figure 18 .
st7liteu05 st7liteu09 interrupts 43/139 8.2 external interrupts external interrupt vectors can be loaded into th e pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt triggered on edge will be latched and th e interrupt request automatically cleared upon entering the interrupt service routine. caution: the type of sensitivity defined in the miscellaneous or interrupt register (if available) applies to the ei source. in case of a nanded source (as described in the i/o ports section), a low level on an i/o pin, configured as input with interrupt, masks the interrupt request even in case of rising-edge sensitivity. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing ?0? to the corresponding bit in the status register or access to the status register while the flag is set followed by a read or write of an associated register. note: the clearing sequence resets the internal latch. a pending interrupt (that is, waiting for being enabled) will therefor e be lost if the clear sequence is executed. figure 18. interrupt processing flowchart i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending?
interrupts st7liteu05 st7liteu09 44/139 table 10. interrupt mapping n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu auto wakeup interrupt awucsr yes (1) 1. this interrupt exits the mcu from ?auto wake-up from halt? mode only. fffah-fffbh 1 ei0 external interrupt 0 n/a yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 2) ei2 (2) 2. whatever the sensitivity confi guration, this interrupt cannot exit the mcu from halt, active-halt and awufh modes when a falling edge occurs. external interrupt 2 (2) fff4h-fff5h 4 not used no fff2h-fff3h 5 ei3 external interrupt 3 yes fff0h-fff1h 6 3) ei4 (3) 3. this interrupt exits the mcu from ?wait? and ?activ e-halt? modes only. moreover is4[1:0] =01 is the only safe configuration to avoid spurious interrupt in halt and awufh modes. external interrupt 4 (3) no (3) ffeeh-ffefh 7 si avd interrupt sicsr no ffech-ffedh 8 at t i m e r at timer output compare interrupt pwmxcsr or atcsr no ffeah-ffebh 9 at timer overflow interrupt atcsr yes (4) 4. these interrupts exit the mcu from ?active-halt? mode only. ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc1 interrupt ltcsr yes (4) ffe4h-ffe5h 12 not used no ffe2h-ffe3h 13 not used no ffe0h-ffe1h
st7liteu05 st7liteu09 interrupts 45/139 8.3.1 external interrupt c ontrol register 1 (eicr1) reset value: 0000 0000 (00h) bits 7:6 = reserved, must be kept cleared. bits 5:4 = is2[1:0] ei2 sensitivity bits these bits define the interrupt sensitivity for ei2 (port c) according to ta b l e 1 1 . bits 3:2 = is1[1:0] ei1 sensitivity bits these bits define the interrupt sensitivity for ei1 (port b) according to ta bl e 1 1 . bits 1:0 = is0[1:0] ei0 sensitivity bits these bits define the interrupt sensitivity for ei0 (port a) according to ta bl e 1 1 . note: 1 these 8 bits can be written only when the i bit in the cc register is set. 2 changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to ?external interrupt function? on page 61. 3 whatever the sensitivity configuration, ei2 cannot exit the mcu from halt, active-halt and awufh modes when a falling edge occurs. 8.3.2 external interrupt c ontrol register 2 (eicr2) reset value: 0000 0000 (00h) bits 7:4 = reserved bits 3:2 = is4[1:0] ei4 sensitivity these bits define the interrupt sensitivity for ei1 according to ta bl e 1 1 . bits 1:0 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei0 according to ta bl e 1 1 . 7 0 0 0 is21 is20 is11 is10 is01 is00 read/write table 11. interrupt sensitivity bits isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 7 0 0 0 0 0 is41 is40 is31 is30 read/write
interrupts st7liteu05 st7liteu09 46/139 note: 1 these 8 bits can be written only when the i bit in the cc register is set. 2 changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to section ?external interrupt function? on page 61. 3 is4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in halt and awufh modes. 8.4 system integrity management (si) the system integrity management block contains the low voltage detector (lvd) and auxiliary voltage detector (avd) functions . it is managed by the sicsr register. note: a reset can also be triggered following the detection of an illegal op code or prebyte code. refer to section 12.2.1 on page 92 for further details. 8.4.1 low voltage detector (lvd) the low voltage detector function (lvd) generates a static reset when the v dd supply voltage is below a v it-(lvd) reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it-(lvd) reference value for a voltage drop is lower than the v it+(lvd) reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v it+(lvd) when v dd is rising v it-(lvd) when v dd is falling the lvd function is illustrated in figure 19 . the voltage threshold can be configured by option byte to be low, medium or high. see section 15.1 on page 127 . provided the minimum v dd value (guaranteed for the osc illator frequency) is above v it-(lvd) , the mcu can only be in two modes: under full software control in static safe reset in these conditions, secure operation is always ensured for the application without the need for external reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices.
st7liteu05 st7liteu09 interrupts 47/139 note: use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 67 on page 118 and note 4. the lvd is an optional function which can be selected by option byte. see section 15.1 on page 127 . it allows the device to be used without any external reset circuitry. if the lvd is disabled, an external circuitry must be used to ensure a proper power-on reset. it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. make sure the right combination of lvd and avd thresholds is used as lvd and avd levels are not correlated. refer to section 13.3.2 on page 98 and section 13.3.3 on page 98 for more details. caution: if an lvd reset occurs after a watchdog reset has occurred, the lvd w ill take priority and will clear the watchdog flag. figure 19. low voltage detector vs reset figure 20. reset and supply management block diagram 8.4.2 auxiliary voltage detector (avd) the voltage detector function (avd) is ba sed on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main supply voltage (v avd ). the v it-(avd) reference value for falling voltage is lower than the v it+(avd) reference value for rising voltage in order to avoid parasitic detection (hysteresis). the output of the avd comparator is directly readable by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. v dd v it+ (lvd) reset v it- (lvd) v hys low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog sicsr timer (wdg) avd avd lvd rf ie 0 f 0 status flag 1 1 7 0 0
interrupts st7liteu05 st7liteu09 48/139 monitoring the v dd main supply. the avd threshold is selected by the avd[1:0] bits in the avdthcr register. if the avd interrupt is enabled, an interrupt is generated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcontroller. see figure 21 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over note: make sure the right combination of lvd and avd thresholds is used as lvd and avd levels are not correlated. refer to section 13.3.2 on page 98 and section 13.3.3 on page 98 for more details. figure 21. using the avd to monitor v dd 8.4.3 low power modes interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is reset (rim instruction). v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interrupt cleared by reset table 12. description of low power modes mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. the avd remains active but the avd interrupt cannot be used to exit from halt mode.
st7liteu05 st7liteu09 interrupts 49/139 8.4.4 register description system integrity (si) control/status register (sicsr) reset value: 0000 0x00 (0xh) bit 7 = reserved, must be kept cleared. bits 6:5 = cr[1:0] rc oscillator frequency adjustment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain the requ ired accuracy. refer to section 7.2 on page 32 . bits 4:3 = reserved, must be kept cleared. bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generated by the lvd block. it is set by hardware (lvd reset) and cleared when read. see wdgrf flag description in section 11.1 on page 68 for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. note: if the selected clock source is one of the two internal ones, and if v dd remains below the selected lvd threshol d during less than t awu_rc (33 s typ.), the lvdrf flag cannot be set even if the device is reset by the lvd. if the selected clock source is the external clock (clkin), the flag is never set if the reset occurs during halt mode. in run mode the flag is set only if f clkin is greater than 10 mhz. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is generated when the avdf bit is set. refer to figure 21 for additional details; 0: v dd over avd threshold 1: v dd under avd threshold bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automatically cleared when software enters the avd interrupt routine. 0: avd interrupt disabled 1: avd interrupt enabled table 13. description of interrupt events interrupt event event fl ag enable control bit exit from wait exit from halt avd event avdf avdie yes no 7 0 0 cr1 cr0 0 0 lvdrf avdf avdie read/write
interrupts st7liteu05 st7liteu09 50/139 avd threshold selection register (avdthcr) reset value: 0000 0011 (03h) bits 7:5 = ck[2:0] internal rc prescaler selection refer to section 7.2 on page 32 . bits 4:2 = reserved, must be kept cleared. bits 1:0 = avd[1:0] avd threshold selection these bits are set and cleared by software and set by hardware after a reset. they select the avd threshold. note: application notes the lvdrf flag is not cleared when another reset type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the original failure. in this case, a watchdog reset can be detected by software while an external reset can not. 7 0 ck2 ck1 ck0 0 0 0 avd1 avd0 read/write table 14. avd threshold selection bits avd1 avd0 functionality 00 low 01 medium 1 0 high 11 avd off table 15. system integrity register map and reset values address (hex.) register label 76543210 003ah sicsr reset value 01100 lvdrf x avdf 0 avdie 0 003eh avdthcr reset value ck2 0 ck1 0 ck0 0 000 avd1 1 avd2 1
st7liteu05 st7liteu09 power saving modes 51/139 9 power saving modes 9.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 22 ): slow wait (and slow-wait) active-halt auto-wakeup from halt (awufh) halt after a reset the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main os cillator frequency (f osc ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. figure 22. power saving mode transitions 9.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillator fr equency is divided by 32. the cpu and peripherals are clocked at this lower frequency. note: slow-wait mode is activated when entering wa it mode while the device is already in slow mode. power consumption wait slow run active halt high low slow wait halt
power saving modes st7liteu05 st7liteu09 52/139 figure 23. slow mode clock transition 9.3 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. du ring wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 24 . figure 24. wait mode flowchart note: 1 before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. sms f cpu normal run mode request f osc f osc /32 f osc wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x 1) on 256 or 512 cpu clock delay cycle
st7liteu05 st7liteu09 power saving modes 53/139 9.4 active-halt and halt modes active-halt and halt modes are the two lowest power consumption modes of the mcu. they are both entered by executing the ?halt? instruction. the decision to enter either in active- halt or halt mode is given by the ltcsr/atcs r register status as shown in the following table: 9.4.1 active-halt mode active-halt mode is the lowest power consumption mode of the mcu with a real time clock available. it is entered by ex ecuting the ?halt? instruction wh en active halt mode is enabled. the mcu can exit active-halt mode on reception of a lite timer / at timer interrupt or a reset. when exiting active-halt mode by means of a reset, a 256 or 512 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 26 ). when exiting active-halt mode by means of an interrupt, the cpu immediately resumes operation by servicing the inte rrupt vector which woke it up (see figure 26 ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and the selected timer counter (lt/at) are running to keep a wake-up time base. all ot her peripherals are not clocked except those which get their clock supply from another cloc k generator (such as external or auxiliary oscillator). caution: as soon as active-halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset if the wdghalt bit is reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 25. active-halt timing overview table 16. enabling/disabling active-halt and halt modes ltcsr tbie bit atcsr ovfie bit atcsrck1 bit atcsrck0 bit meaning 0xx0 active-halt mode disabled 00xx 0111 1xxx active-halt mode enabled x101 halt run run 256 or 512 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled]
power saving modes st7liteu05 st7liteu09 54/139 figure 26. active-halt mode flowchart 1. this delay occurs only if the mcu exit s active-halt mode by means of a reset. 2. peripherals clocked with an external clock source can still be active. 3. only the lite timer rtc and at timer interru pts can exit the mcu from active-halt mode. 4. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 9.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the ?halt? instruction when active halt mode is disabled. the mcu can exit halt mode on reception of either a specific interrupt (see ta bl e 1 0 : interrupt mapping on page 44 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the main oscillator is immediat ely turned on and t he 256 or 512 cpu cycle delay is used to stabilize it. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 28 ). when entering halt mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immediately. in halt mode, the main oscillator is turned off causing all intern al processing to be stopped, including the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of watc hdog operation with halt mode is configured by the ?wdghalt? option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see section 15.1 on page 127 for more details). halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) ibit on off x 4) on cpu oscillator peripherals ibits on on x 4) on 256 or 512 cpu clock delay (active halt enabled) cycle
st7liteu05 st7liteu09 power saving modes 55/139 figure 27. halt timing overview figure 28. halt mode flowchart 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 10, ?interrupt mapping,? on page 44 for more details. 4. before servicing an interrupt, the cc register is pus hed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 5. the cpu clock must be switched to 1 mhz ( rc/8) or awu rc before entering halt mode. halt mode recommendations make sure that an external event is available to wake up the microcontroller from halt mode. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt halt run run 256 or 512 delay reset or interrupt halt instruction fetch vector [ active halt disabled ] cpu cycle halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibits on on x 4) on 256 or 512 cpu clock cycle delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 (active halt disabled)
power saving modes st7liteu05 st7liteu09 56/139 instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). 9.5 auto-wakeup from halt mode auto-wake up from halt (awufh) mode is similar to halt mode with the addition of a specific internal rc oscillator for wakeup (a uto-wakeup from halt oscillator) which replaces the main clock which was active before entering halt mode. compared to active-halt mode, awufh has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available. it is entered by executing the halt inst ruction when the awuen bit in the awucsr register has been set. figure 29. awufh mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divider and a programmable prescaler controlled by the awupr register. the output of this prescaler provides the delay time. when the delay has elapsed, the following actions are performed: the awuf flag is set by hardware, an interrupt wakes-up the mcu from halt mode, the main oscillator is immediately turned on and the 256 or 512 cpu cycle delay is used to stabilize it. after this start-up delay, the cpu resumes ope ration by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler/1 .. 255 interrupt /64 divider to 8-bit timer input capture
st7liteu05 st7liteu09 power saving modes 57/139 mode. this connects f awu_rc to the input capture of the 8-bit lite timer, allowing the f awu_rc to be measured using the main oscillator cloc k as a reference timebase. similarities with halt mode the following awufh mode behaviour is the same as normal halt mode: the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a reset (see section 9.4: active-halt and halt modes on page 53 ). when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in awufh mode, the main oscilla tor is turned off causing a ll internal processing to be stopped, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the awu oscillator). the compatibility of watchdog operation wi th awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset. figure 30. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 256 or 512 t cpu run mode f awu_rc clear by software t awu
power saving modes st7liteu05 st7liteu09 58/139 figure 31. awufh mode flowchart 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrupt and some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 10, ?interrupt mapping,? on page 44 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of the inte rrupt routine and recovered when the cc register is popped. 9.5.1 register description awufh control/status register (awucsr) reset value: 0000 0000 (00h) bits 7:3 = reserved reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 256 or 512 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active-halt disabled) (awucsr.awuen=1) 7 0 00000awufawumawuen read/write
st7liteu05 st7liteu09 power saving modes 59/139 bit 2 = awuf auto wake up flag this bit is set by hardware when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1 = awum auto wake up measurement bit this bit enables the awu rc oscillator and co nnects its output to the input capture of the 8-bit lite timer. this allows the timer to be used to measur e the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupre register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake up from halt enabled bit this bit enables the auto wake up from halt feature: once halt mode is entered, the awufh wakes up the microcontroller after a time delay dependent on the awu prescaler value. it is se t and cleared by software. 0: awufh (auto wake up from halt) mode disabled 1: awufh (auto wake up from halt) mode enabled note: whatever the clock source, this bit should be set to enable the awufh mode once the halt instruction has been executed. awufh prescaler register (awupr) reset value: 1111 1111 (ffh) bits 7:0= awupr[7:0] auto wakeup prescaler these 8 bits define the awupr dividing factor (see ta b l e 1 7 ). in awu mode, the time during which the mcu stays in halt mode, t awu , is given by the equation below. see also figure 30 on page 57 . 7 0 awupr7 awupr6 awupr5 awupr4 awupr3 awupr2 awupr1 awupr0 read/write table 17. configuring the dividing factor awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255
power saving modes st7liteu05 st7liteu09 60/139 the awupr prescaler register can be programmed to modify the time during which the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on th e product, an interrupt is generated immediately after a halt instruction, or the awupr remains unchanged. t awu 64 awupr 1 f awurc -------------------- t rcstrt + = table 18. awu register map and reset values address (hex.) register label 76543210 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 004ah awucsr reset value 00000awufawumawuen
st7liteu05 st7liteu09 i/o ports 61/139 10 i/o ports 10.1 introduction the i/o port offers different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip peripherals. an i/o port contains up to 6 pins. each pin (except pa3/reset) can be programmed independently as digital input (with or without interrupt generation) or digital output. 10.2 functional description each port has 2 main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corresponding register bits in the ddr and or registers: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not provide this register refer to the i/o port implementation section). the generic i/o block diagram is shown in figure 32 . 10.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note: 1 writing the dr register modifies the latch value but does not affect the pin status. 2 pa3 cannot be configured as input. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedicated group of i/o port pins (see pinout description and interrupt section). if several i/o interrupt pins on the same interrupt vector are selected simultaneously, they are logically combined. for this reason if one of the interrupt pins is tied low, it may mask the others.
i/o ports st7liteu05 st7liteu09 62/139 external interrupts are hardware interrupts. fetching the corresponding interrupt vector automatically clears the request latch. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. spurious interrupts when enabling/disabling an external interrupt by setting/resetting the related or register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. this is due to the edge dete ctor input which is s witched to '1' when the external interrupt is disabled by the or register. to avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the or register bit and configuring the appropriate sensitivity again. caution: in case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. this corresponds to the following steps: 1. to enable an external interrupt: a) set the interrupt mask with the sim instruction (in cases where a pin level change could occur) b) select rising edge c) enable the external interrupt through the or register d) select the desired sensitivity if different from rising edge e) reset the interrupt mask with the rim instruction (in cases where a pin level change could occur) 2. to disable an external interrupt: a) set the interrupt mask with the sim instruction sim (in cases where a pin level change could occur) b) select falling edge c) disable the external interrupt through the or register d) select rising edge 10.2.2 output modes the output conf iguration is selected by setting the co rresponding ddr regist er bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain.
st7liteu05 st7liteu09 i/o ports 63/139 note: when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 10.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over the standard i/o programming under the following conditions: when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip perip heral, the i/o pin must be configured in floating input mode. in this case, the pin st ate is also digitally readable by addressing the dr register. note: input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. table 19. dr value and output pin status dr push-pull open-drain 0v ss vss 1v dd floating
i/o ports st7liteu05 st7liteu09 64/139 figure 32. i/o port general block diagram table 20. i/o port mode options (1) 1. off means implemented not activat ed, on means implemented and activated. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access
st7liteu05 st7liteu09 i/o ports 65/139 table 21. i/o port configurations caution: the alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. 10.2.4 analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. caution: the analog input voltage level must be within the limits stated in the absolute maximum ratings. hardware configuration input (1) 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read th e alternate function output status. open-drain output (2) 2. when the i/o port is in output configuration and t he associated alternate func tion is enabled as an input, the alternate function reads the pin stat us given by the dr register content. push-pull output (2) condition pad v dd r pu external interrupt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register condition alternate input analog input pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register pad r pu data bus dr dr register access r/w v dd alternate alternate enable output register
i/o ports st7liteu05 st7liteu09 66/139 10.3 unused i/o pins unused i/o pins must be connected to fixed voltage levels. refer to section 13.8 on page 109 . 10.4 low power modes 10.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). 10.6 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr and or registers and specific feature of the i/o port such as adc input or true open drain. switching these i/o ports from one state to another should be done in a sequence that prevents unwanted side effects. recommend ed safe transitions are illustrated in figure 33 . other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 33. interrupt i/o port state transitions table 22. effect of low power modes on i/o ports mode description wait no effect on i/o ports. external interrup ts cause the device to exit from wait mode. halt no effect on i/o ports. external interrup ts cause the device to exit from halt mode. table 23. description of interrupt events interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx ye s ye s 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or
st7liteu05 st7liteu09 i/o ports 67/139 the i/o port register configurations are summarised in the following table: table 24. port configuration port pin name input (ddr=0) output (ddr=1) or = 0 or = 1 or = 0 or = 1 port a pa0:2, pa4:5 (1) 1. is4[1:0] = 01 is the only safe configuration to av oid spurious interrupt in ha lt and awufh modes. refer to eicr2 description on section 8.3.2 on page 45 . floating pull-up interrupt (1) open drain push-pull pa 3 (2) 2. after reset, to configure pa3 as a general purpos e output, the application has to program the muxcr0 and muxcr1 registers. see section 7.5 on page 41 . - - open drain push-pull table 25. i/o port register map and reset values address (hex.) register label 76543210 0000h pa d r reset value msb 0000000 lsb 0 0001h paddr reset value msb 0000100 lsb 0 0002h pao r reset value msb 0000001 lsb 0
on-chip peripherals st7liteu05 st7liteu09 68/139 11 on-chip peripherals 11.1 lite timer (lt) 11.1.1 introduction the lite timer can be used for general-purpose timing functions. it is based on a free- running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function. 11.1.2 main features real-time clock ? 13-bit upcounter ? 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? maskable timebase interrupt input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wakeup from halt mode capability watchdog ? enabled by hardware or software (configurable by option byte) ? optional reset on halt instruction (configurable by option byte) ? automatically resets the device unless disable bit is refreshed ? software reset (forced watchdog reset) ? watchdog reset status flag
st7liteu05 st7liteu09 on-chip peripherals 69/139 figure 34. lite timer block diagram 11.1.3 functional description the value of the 13-bit counter cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc . a counter overflow event occurs when the counter rolls over from 1f39h to 00h. if f osc = 8 mhz, then the time period between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr register. when the timer overflows, the tbf bit is set by hardware and an interrupt request is generated if the tbie is set. the tbf bit is cleared by software reading the ltcsr register. watchdog the watchdog is enabled using the wdge bit. the normal watchdog timeout is 2ms (@ fosc = 8 mhz ), after which it then generates a reset. to prevent this watchdog reset occuring, software must set the wdgd bit. the wdgd bit is cleared by hardware after t wdg . this means that software must write to the wdgd bit at regular intervals to prevent a watchdog reset occurring. refer to figure 35 . if the watchdog is not enabled immediately af ter reset, the first watchdog timeout will be shorter than 2ms, because this period is counted starting from reset. moreover, if a 2ms period has already elapsed afte r the last mcu reset, the watc hdog reset will take place as soon as the wdge bit is set. for these reasons, it is recommended to enable the watchdog immediately after reset or else to set the wdgd bit before the wgde bit so a watchdog reset will not occur for at least 2 ms. note: software can use the timebase feature to set the wdgd bit at 1 or 2 ms intervals. ltcsr watchdog 13-bit upcounter /2 8-bit f ltimer f wdg 8 msb ltic f osc wdgd wdge wdg tbf tbie tb icf icie watchdog reset lttb interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8 mhz f osc ) to 12-bit at timer f ltimer rf 0 7
on-chip peripherals st7liteu05 st7liteu09 70/139 a watchdog reset can be forced at any time by setting the wdgrf bit. to generate a forced watchdog reset, first watchdog has to be activated by setting the wdge bit and then the wdgrf bit has to be set. the wdgrf bit also acts as a flag, indicating that the watchdog was the source of the reset. it is automatically cleared after it has been read. caution: when the wdgrf bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or so ftware), the microcontrolle r will be immediately reset. 11.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdge bit in the ltcsr is not used. refer to the option byte description in the "device configuration and ordering information" section. using halt mode with the watchdog (option) if the watchdog reset on halt option is not selected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt instruction stops the oscillator. when the oscillator is stopped, the lite timer stops counting and is no longer able to generate a watchdog reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg restarts counting after 256 or 512 cpu clocks. if a reset is generated, the watchdog is disabled (reset state). if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. figure 35. watchdog timing diagram input capture the 8-bit input capture register is used to latc h the free-running upcounter after a rising or falling edge is detected on the lt ic pin. when an input capture occurs, the icf bit is set and the lticr register contains the msb of the free-running upcounter. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read only register and always contains the data from the last input capture. input capture is inhibited if the icf bit is set. t wdg f wdg internal watchdog reset wdgd bit software sets wdgd bit hardware clears wdgd bit watchdog reset (2ms @ 8 mhz f osc )
st7liteu05 st7liteu09 on-chip peripherals 71/139 11.1.5 low power modes 11.1.6 interrupts note: the tbf and icf interrupt events are connected to separate interrupt vectors (see interrupts chapter). they generate an interrupt if the enable bit is set in the ltcsr register and the interrupt mask in the cc register is reset (rim instruction). figure 36. input capture timing diagram table 26. description of low power modes mode description wait no effect on lite timer active-halt no effect on lite timer halt lite timer stops counting table 27. interrupt events interrupt event event flag enable control bit exit from wait exit from halt exit from active-halt timebase event tbf tbie yes no yes ic event icf icie yes no no 0004h 13-bit counter t 0001h f osc xxh 0002h 0003h 0005h 0006h 0007h 04h ltic pin icf flag lticr register cleared 125 ns (@ 8 mhz f osc ) f cpu by s/w 07h reading ltic register
on-chip peripherals st7liteu05 st7liteu09 72/139 11.1.7 register description lite timer control/status register (ltcsr) reset value: 0000 0x00 (0xh) bit 7 = icie interrupt enable. this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, software must initialise the icf bit by reading the lticr register bit 5 = tb timebase period selection. this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1 ms @ 8 mhz) 1: timebase period = t osc * 16000 (2 ms @ 8 mhz) bit 4 = tbie timebase interrupt enable . this bit is set and cleared by software. 0: timebase (tb) interrupt disabled 1: timebase (tb) interrupt enabled bit 3 = tbf timebase interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bit 2 = wdgrf force reset/ reset status flag this bit is used in two ways: it is set by software to force a watchdog reset. it is set by hardware when a watchdog reset occurs and cleared by hardware or by software. it is cleared by hardware only when an lvd reset occurs. it can be cleared by software after a read access to the ltcsr register. 0: no watchdog reset occurred. 1: force a watchdog reset (write), or, a watchdog reset occurred (read). 7 0 icie icf tb tbie tbf wdgr wdge wdgd read / write
st7liteu05 st7liteu09 on-chip peripherals 73/139 bit 1 = wdge watchdog enable this bit is set and cleared by software. 0: watchdog disabled 1: watchdog enabled bit 0 = wdgd watchdog reset delay this bit is set by software. it is cleared by hardware at the end of each t wdg period. 0: watchdog reset not delayed 1: watchdog reset delayed lite timer input capture register (lticr) reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of the 8-bit up-c ounter will be captured when a rising or falling edge occurs on the ltic pin. 7 0 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 read only table 28. lite timer register map and reset values address (hex.) register label76543210 0b ltcsr reset value icie 0 icf 0 tb 0 tbie 0 tbf 0 wdgrf x wdge 0 wdgd 0 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0
on-chip peripherals st7liteu05 st7liteu09 74/139 11.2 12-bit autoreload timer (at) 11.2.1 introduction the 12-bit autoreload timer can be used for gen eral-purpose timing functions. it is based on a free-running 12-bit upcounter with a pwm output channel. 11.2.2 main features 12-bit upcounter with 12-bit autoreload register (atr) maskable overflow interrupt pwm signal generator frequency range 2 khz - 4 mhz (@ 8 mhz f cpu ) ? programmable duty-cycle ? polarity control ? maskable compare interrupt output compare function figure 37. block diagram 11.2.3 functional description pwm mode this mode allows a pulse width modulated signals to be generated on the pwm0 output pin with minimum core processing overhead. the pwm0 output signal can be enabled or disabled using the oe0 bit in the pwmcr register. when this bit is set the pwm i/o pin is configured as output push-pull alternate function. note: cmpf0 is available in pwm mode (see pwm0csr description on page 80 ). atcsr cmpie ovfie ovf ck0 ck1 0 0 0 12-bit autoreload value 12-bit upcounter cmpf0 bit cmpf0 cmp interrupt request ovf interrupt request f cpu atr pwm generation pol- arity op0 bit pwm0 comp- pare f counter f pwm output control oe0 bit cntr (1 ms timebase f ltimer dcr0h dcr0l update on ovf event preload preload @ 8 mhz) 70 on ovf event 0 1 12-bit duty cycle value (shadow) oe0 bit if oe0=1
st7liteu05 st7liteu09 on-chip peripherals 75/139 pwm frequency and duty cycle the pwm signal frequency (f pwm ) is controlled by the counter period and the atr register value. f pwm = f counter / (4096 - atr) following the above formula, if f cpu is 8 mhz, the maximum value of f pwm is 4 mhz (atr register value = 4094), and the minimum value is 2 khz (atr register value = 0). note: the maximum value of atr is 4094 because it must be lower than the dcr value which must be 4095 in this case. at reset, the counter starts counting from 0. software must write the duty cycle value in the dcr0h and dcr0l preload registers. the dcr0h register must be written first. see caution below. when a upcounter overflow occurs (ovf event), the atr value is loaded in the upcounter, the preloaded duty cycle value is transferred to the duty cycle register and the pwm0 signal is set to a high level. when the upcounter matches the dcrx value the pwm0 signals is set to a low level. to obtain a signal on the pwm0 pin, the contents of the dcr0 register must be greater than the contents of the atr register. the polarity bit can be used to invert the output signal. the maximum available resoluti on for the pwm0 duty cycle is: resolution = 1 / (4096 - atr) note: to get the maximum resolution (1/4096), the atr register must be 0. with this maximum resolution and assuming that dcr=atr, a 0% or 100% duty cycle can be obtained by changing the polarity . caution: as soon as the dcr0h is written, the compare function is disabled and will start only when the dcr0l value is written. if the dcr0h write occurs just before the compare event, the signal on the pwm output may not be set to a low level. in this case, the dcrx register should be updated just after an ovf event. if the dcr and atr values are close, then the dcrx register shouldbe updated just before an ovf event, in order not to miss a compare event and to have the right signal applied on the pwm output. figure 38. pwm function duty cycle register auto-reload register pwm0 output t 4095 000 with oe0=1 and op0=0 (atr) (dcr0) with oe0=1 and op0=1 counter
on-chip peripherals st7liteu05 st7liteu09 76/139 figure 39. pwm signal example output compare mode to use this function, the oe bit must be 0, otherwise the compare is done with the shadow register instead of the dcrx register. software must then write a 12-bit value in the dcr0h and dcr0l registers. this value will be load ed immediately (without waiting for an ovf event). the dcr0h must be written first, the output compare function starts only when the dcr0l value is written. when the 12-bit upcounter (cntr) reaches the value stored in the dcr0h and dcr0l registers, the cmpf0 bit in the pwm0csr register is set and an interrupt request is generated if the cmpie bit is set. note: the output compare function is only available for dcrx values other than 0 (reset value). caution: at each ovf event, the dcrx value is written in a shadow register, even if the dcr0l value has not yet been written (in this case, the sh adow register will contain the new dcr0h value and the old dcr0l value), then: - if oe=1 (pwm mode): the compare is done between the timer counter and the shadow register (and not dcrx) - if oe=0 (ocmp mode): the compare is done between the timer counter and dcrx. there is no pwm signal. the compare between dcrx or the shadow register and the timer counter is locked until dcr0l is written. counter pwm0 output t with oe0=1 and op0=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcr0=ffeh atr= ffdh f counter
st7liteu05 st7liteu09 on-chip peripherals 77/139 11.2.4 low power modes 11.2.5 interrupts 11.2.6 register description timer control status register (atcsr) reset value: 0000 0000 (00h) bits 7:5 = reserved, must be kept cleared. bits 4:3 = ck[1:0] counter clock selection. these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. table 29. description of low power modes mode description slow the input frequency is divided by 32 wait no effect on at timer active-halt at timer halted except if ck0=1, ck1=0 and ovfie=1 halt at timer halted table 30. interrupt events interrupt event (1) 1. the interrupt events are connected to separat e interrupt vectors (see interrupts chapter). they generate an interrupt if the enable bit is set in the atcs r register and the interrupt mask in the cc register is reset (rim instruction). event flag enable control bit exit from wait exit from halt exit from active-halt overflow event ovf ovfie yes no yes (2) 2. only if ck0=1 and ck1=0 cmp event cmpfx cmpie yes no no 7 0 0 0 0 ck1 ck0 ovf ovfie cmpie read/write table 31. counter clock selection counter clock selection ck1 ck0 off 0 0 f lt i m e r (1 ms timebase @ 8 mhz) 0 1 f cpu 10 reserved 1 1
on-chip peripherals st7liteu05 st7liteu09 78/139 bit 2 = ovf overflow flag. this bit is set by hardware and cleared by software by reading the atcsr register. it indicates the transition of the counter from fffh to atr value. 0: no counter overflow occurred 1: counter overflow occurred caution: when set, the ovf bit stays high for 1 f counter cycle (up to 1ms depending on the clock selection) after it has been cleared by software. bit 1 = ovfie overflow interrupt enable. this bit is read/write by software and cleared by hardware after a reset. 0: ovf interrupt disabled 1: ovf interrupt enabled bit 0 = cmpie compare interrupt enable . this bit is read/write by software and clear by hardware after a reset. it allows to mask the interrupt generation when cmpf bit is set. 0: cmpf interrupt disabled 1: cmpf interrupt enabled counter register high (cntrh) reset value: 0000 0000 (00h) counter register low (cntrl) reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = cntr[11:0] counter value . this 12-bit register is read by software and cleared by hardware after a reset. the counter is incremented continuously as soon as a counter clock is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations. as there is no latch, it is recommended to read lsb first. in this case, cntrh can be incremented between the two read operations and to have an accurate result when f timer = f cpu , special care must be taken when cntrl values close to ffh are read. when a counter overflow occurs, the counter restarts from the value specified in the at r r e g i s t e r. 15 8 0 0 0 0 cn11 cn10 cn9 cn8 read only 7 0 cn7 cn6 cn5 cn4 cn3 cn2 cn1 cn0 read only
st7liteu05 st7liteu09 on-chip peripherals 79/139 auto reload register (atrh) reset value: 0000 0000 (00h) auto reload register (atrl) reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = atr[11:0] autoreload register. this is a 12-bit register which is writte n by software. the atr register value is automatically loaded into the upcounter when an overflow occurs. the register value is used to set the pwm frequency. pwm0 duty cycle register high (dcr0h) reset value: 0000 0000 (00h) pwm0 duty cycle register low (dcr0l) reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = dcr[11:0] pwmx duty cycle value this 12-bit value is written by software. the high register must be written first. in pwm mode (oe0=1 in the pwmcr regi ster) the dcr[11 :0] bits define the duty cycle of the pwm0 output signal (see figure 38 ). in output compare mode, (oe0=0 in the pwmcr register) they define the value to be compared with the 12-bit upcounter value. 15 8 0000atr11atr10atr9atr8 read/write 7 0 at r 7 at r 6 at r 5 at r 4 at r 3 at r 2 at r 1 at r 0 read/write 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 read/write 7 0 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 read/write
on-chip peripherals st7liteu05 st7liteu09 80/139 pwm0 control/status register (pwm0csr) reset value: 0000 0000 (00h) bit 7:2 = reserved, must be kept cleared. bit 1 = op0 pwm0 output polarity. this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm0 signal. 0: the pwm0 signal is not inverted. 1: the pwm0 signal is inverted. bit 0 = cmpf0 pwm0 compare flag. this bit is set by hardware and cleared by software by reading the pwm0csr register. it indicates that the upcounter value matches the dcr0 register value. 0: upcounter value does not match dcr value. 1: upcounter value matches dcr value. pwm output control register (pwmcr) reset value: 0000 0000 (00h) bits 7:1 = reserved, must be kept cleared. bit 0 = oe0 pwm0 output enable . this bit is set and cleared by software. 0: pwm0 output alternate function disabled (i/o pin free for general purpose i/o) 1: pwm0 output enabled 7 0 000000op0cmpf0 read/write 7 0 0000000oe0 read/write table 32. register map and reset values address (hex.) register label 76543210 0d atcsr reset value 000 ck1 0 ck0 0 ovf 0 ovfie 0 cmpie 0 0e cntrh reset value 0000 cn11 0 cn10 0 cn9 0 cn8 0 0f cntrl reset value cn7 0 cn6 0 cn5 0 cn4 0 cn3 0 cn2 0 cn1 0 cn0 0 10 atrh reset value 0000 at r 1 1 0 at r 1 0 0 at r 9 0 at r 8 0
st7liteu05 st7liteu09 on-chip peripherals 81/139 11.3 10-bit a/d converter (adc) 11.3.1 introduction the on-chip analog to digital converter (adc) peripheral is a 10-bit, successive approximation converter with intern al sample and hold circuitry. this peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 11.3.2 main features 10-bit conversion up to 5 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 40 . 11.3.3 functional description analog power supply v dd and v ss are the high and low level reference voltage pins. 11 atrl reset value at r 7 0 at r 6 0 at r 5 0 at r 4 0 at r 3 0 at r 2 0 at r 1 0 at r 0 0 12 pwmcr reset value 0000000 oe0 0 13 pwm0csr reset value 000000 op 0 cmpf0 0 17 dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 table 32. register map and reset values (continued) address (hex.) register label 76543210
on-chip peripherals st7liteu05 st7liteu09 82/139 conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 40. adc block diagram digital a/d conversion result the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dd (high-level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the adcdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ss (low-level voltage reference) then the conversion result in the adcdrh and ad cdrl registers is 00 00h. the a/d converter is linear and the digital result of the conv ersion is stored in the adcdrh and adcdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the alloted time. a/d conversion phases the a/d conversion is based on two conversion phases: 1. sample capacitor loading [duration: t sample ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. 2. a/d conversion [duration: t hold ] during this phase, the a/d conversion is computed (8 successive approximations ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 0 slow 0 0 r adc c adc hold control f adc f cpu 0 1 1 0 div 2 div 4 slow bit
st7liteu05 st7liteu09 on-chip peripherals 83/139 cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. the total conversion time: t conv = t sample + t hold while the adc is on, these two phases are continuously repeated. at the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. a/d conversion the analog input ports must be configured as input, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inpu ts does not affect the ab ility of the port to be read as a logic input. in the adccsr register: select the cs[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the eoc bit is set by hardware. the result is in the adcdr registers. a read to the adcdrh or a write to any bit of the adccsr register resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read adcdrl 3. read adcdrh. this cl ears eoc automatically. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this cl ears eoc automatically. changing the conversion channel the application can change channels during conversion. when software modifies the ch[2:0] bits in the adccsr register, the current conversion is stopped, the eoc bit is cleared, and the a/d converter starts converting the newly selected channel.
on-chip peripherals st7liteu05 st7liteu09 84/139 11.3.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.3.5 interrupts none. 11.3.6 register description adc control/status register (adccsr) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by hardware when software reads the adcdrh register or writes to any bit of the adccsr register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit description. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bits 4:3 = reserved. must be kept cleared. bits 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. table 33. effect of low power modes mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time t stab (see electrical characteristics) before accurate conversions can be performed. 7 0 eoc speed adon 0 0 ch2 ch1 ch0 read/write (except bit 7 read only)
st7liteu05 st7liteu09 on-chip peripherals 85/139 note: a write to the adccsr register (with adon set) aborts the current conversion, resets the eoc bit and starts a new conversion. adc data register high (adcdrh) reset value: 0000 0000 (00h) adc control/data register low (adcdrl) reset value: 0000 0000 (00h) bits 7:5 = reserved . forced by hardware to 0. bit 4 = reserved . forced by hardware to 0. bit 3 = slow slow mode this bit is set and cleared by software. it is used together wit h the speed bit to configure the adc clock speed as shown on the table below. bit 2 = reserved. forced by hardware to 0. table 34. channel selection channel pin ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 7 0 d9 d8 d7 d6 d5 d4 d3 d2 read only 7 0 0000slow0d1d0 read/write table 35. configuring the adc clock speed f adc slow speed f cpu /2 0 0 f cpu 01 f cpu /4 1 x
on-chip peripherals st7liteu05 st7liteu09 86/139 bits 1:0 = d[1:0] lsb of analog converted value table 36. adc register map and reset values address (hex.) register label 76543210 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0036h adcdrl reset value 0 0 0 0 0 0 0 0 slow 0 0 0 d1 0 d0 0
st7liteu05 st7liteu 09 instruction set 87/139 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in seven main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two submodes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 37. description of addressing modes addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 38. st7 addressing mode overview mode syntax destination/ source pointer address pointer size length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10 ],x) 00..1fe 00..ff byte + 2
instruction set st7liteu05 st7liteu09 88/139 note: 1 at the time the instruction is executed, the program counter (pc) points to the instruction following jrxx. 12.1.1 inherent mode all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 table 38. st7 addressing mode overview (continued) mode syntax destination/ source pointer address pointer size length (bytes) table 39. instructions supporting inherent addressing mode inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret subroutine return iret interrupt subroutine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication
st7liteu05 st7liteu 09 instruction set 89/139 12.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two submodes: direct (short) addressing mode the address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - ff addressing space. direct (long) addressing mode the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 indexed mode ( no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: indexed mode (no offset) there is no offset (no extra byte after the opcode), and allows 00 - ff addressing space. indexed mode (short) the offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1fe addressing space. sll, srl, sra, rlc, rrc sh ift and rotate operations swap swap nibbles table 39. instructions supporting inherent addressing mode (continued) inherent instruction function table 40. instructions supporting inherent immediate addressing mode immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
instruction set st7liteu05 st7liteu09 90/139 indexed mode (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 indirect modes (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two submodes: indirect mode (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect mode (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 12.1.6 indirect indexed modes (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed mode (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed mode (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 41. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes instructions function long and short instructions ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtraction operations bcp bit compare
st7liteu05 st7liteu 09 instruction set 91/139 12.1.7 relative modes (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two submodes: relative mode (direct) the offset follows the opcode. relative mode (indirect) the offset is defined in memory, of which the address follows the opcode. 12.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: short instructions only clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine table 41. instructions supporting direct, i ndexed, indirect and indirect indexed addressing modes (continued) instructions function table 42. instructions supporting relative modes available relative direct/ind irect instructions function jrxx conditional jump callr call relative table 43. st7 instruction set load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp
instruction set st7liteu05 st7liteu09 92/139 using a prebyte the instructions are described with 1 to 4 bytes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. 12.2.1 illegal opcode reset in order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implem ented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf table 43. st7 instruction set (continued)
st7liteu05 st7liteu 09 instruction set 93/139 table 44. illegal opcode detection mnemo description functi on/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >=
instruction set st7liteu05 st7liteu09 94/139 jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7.. 4]<=>dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 44. illegal opcode detection (continued) mnemo description functi on/example dst src h i n z c
st7liteu05 st7liteu09 elec trical characteristics 95/139 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd = 5 v (for the 4.5 v v dd 5.5 v voltage range), v dd = 3.75 v (for the 3 v v dd 4.5 v voltage range) and v dd =2.7 v (for the 2.4 v v dd 3 v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 41 . figure 41. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 42 . c l st7 pin
electrical characteristics st7liteu05 st7liteu09 96/139 figure 42. pin input voltage 13.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in st7 pin table 45. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 7.0 v v in input voltage on any pin (1)(2) v ss -0.3 to v dd +0.3 v esd(hbm) electrostatic discharge voltage (human body model) see section 13.7.3 on page 108 v esd(mm) electrostatic discharge voltage (machine model) 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpect ed change of the i/o configuration occurs (for example, due to a corrupt ed program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10 k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if vi n maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the iinj(pin) val ue. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7liteu05 st7liteu09 elec trical characteristics 97/139 13.3 operating conditions 13.3.1 general operating conditions t a = -40 to +125 c unless otherwise specified. figure 43. f cpu maximum operating frequency versus v dd supply voltage 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st7liteu05 st7liteu09 98/139 13.3.2 operating conditions with low voltage detector (lvd) t a = -40 to 125 c, unless otherwise specified 13.3.3 auxiliary voltage detector (avd) thresholds t a = -40 to 125c, unless otherwise specified note: refer to ?monitoring the vdd main supply.? on page 48. table 49. operating characteristics with lvd symbol parameter conditions min typ max unit v it+ (lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 3.9 3.2 2.5 4.2 3.5 2.7 4.5 3.8 3.0 v v it- (lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.7 3.0 2.4 4.0 3.3 2.6 4.3 3.6 2.9 v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 150 mv vt por v dd rise time rate (1)(2) 1. not tested in production. the v dd rise time rate condition is needed to ensure a correct device power-on and lvd reset release. when the v dd slope is outside these values, the lvd may not release properly the reset of the mcu 2. use of lvd with capacitive power supply: with this type of pow er supply, if power cuts occu r in the application, it is recommended to pull v dd down to 0v to ensure optimum restart c onditions. refer to circuit example in figure 66 on page 117 . 20 s/v i dd(lvd) (3) 3. not tested in production. lvd/avd current consumption v dd = 5v 220 a table 50. operating characteristics with avd symbol parameter conditions min (1) 1. not tested in production, guar anteed by characterization. typ (1) max (1) unit v it+ (avd) 1 => 0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 4.0 3.4 2.6 4.4 3.7 2.9 4.8 4.1 3.2 v v it- (avd) 0 => 1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 3.9 3.3 2.5 4.3 3.6 2.8 4.7 4.0 3.1 v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) 150 mv
st7liteu05 st7liteu09 elec trical characteristics 99/139 13.3.4 internal rc oscillator to improve clock stability and frequency accura cy, it is recommended to place a decoupling capacitor, typically 100 nf, between the v dd and v ss pins as close as possible to the st7 device internal rc oscillator calibrated at 5.0 v the st7 internal clock can be supplied by an internal rc oscillator (selectable by option byte). table 51. voltage drop between avd flag set and lvd reset generation parameter min (1) 1. not tested in production, guar anteed by characterization. typ (1) max (1) unit avd med. threshold - avd low. threshold 800 850 950 mv avd high. threshold - avd low threshold 1400 1450 1550 avd high. threshold - avd med. threshold 600 650 750 avd low threshold - lvd low threshold 100 200 250 avd med. threshold - lvd low threshold 950 1050 1150 avd med. threshold - lvd med. threshold 250 300 400 avd high. threshold - lvd low threshold 1600 1700 1800 avd high. threshold - lvd med. threshold 900 1000 1050 table 52. internal rc oscillator characteristics (5.0 v calibration) symbol parameter conditions min typ max unit f rc internal rc oscillator frequency rccr = ff (reset value), t a = 25 c, v dd = 5 v 4.4 mhz rccr = rccr0 (1) , t a = 25 c, v dd = 5 v 8 acc rc accuracy of internal rc oscillator with rccr=rccr0 (1) t a = 25 c, v dd = 4.5 to 5.5 v (2) -2.0 +2.0 % t a = 0 to +85 c, v dd = 4.5 to 5.5 v (2) -2.5 +4.0 % t a = 0 to +125 c, v dd = 4.5 to 5.5 v (2) -3.0 +5.0 % t a = -40 c to 0 c, v dd = 4.5 to 5.5 v (2) -4.0 +2.5 % t su(rc) rc oscillator setup time t a = 25c, v dd = 5 v 4 (2) s 1. see ?internal rc oscillator adjustment? on page 32 2. tested in production at 5.0 v only
electrical characteristics st7liteu05 st7liteu09 100/139 internal rc oscillator calibrated at 3.3 v the st7 internal clock can be supplied by an internal rc oscillator (selectable by option byte). figure 44. typical accuracy with rccr=rccr0 vs v dd = 2.4-6.0 v and temperature figure 45. typical accuracy with rccr=rccr1 vs v dd = 2.4-6.0v and temperature table 53. internal rc oscillator characteristics (3.3 v calibration) symbol parameter conditions min typ max unit f rc internal rc oscillator frequency rccr = ff (reset value), t a =25 c,v dd = 3.3 v 4.3 mhz rccr = rccr1 (1) , t a =25 c,v dd = 3.3 v 8 acc rc accuracy of internal rc oscillator with rccr=rccr1 (1) t a =25c, v dd = 3.0 to 3.6 v (2) -1.0 +1.0 % t a =0 to +85 c, v dd = 3.0 to 3.6 v (2) -2.5 +4.0 % t a =0 to +125 c, v dd = 3.0 to 3.6 v (2) -3.0 +5.0 % t a = -40 c to 0 c, v dd = 3.0 to 3.6 v (2) -4.0 +2.5 % t su(rc) rc oscillator setup time t a = 25 c, v dd = 3.3 v 4 (2) s 1. see ?internal rc oscillator adjustment? on page 32 2. tested in production at 3.3 v only -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 accuracy (%) rc5v@-45c rc5v@25c rc5v@90c rc5v@130c rc5v@0c -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 accuracy (%) rc3.3v@-45c rc3.3v@25c rc3.3v@90c rc3.3v@130c rc3.3v@0c
st7liteu05 st7liteu09 elec trical characteristics 101/139 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). refer to section 13.4.2: internal rc oscillator supply characteristics on page 102 . 13.4.1 supply current t a = -40 to +125c unless otherwise specified table 54. supply current characteristics symbol parameter conditions typ max unit i dd supply current in run mode (1) v dd =5v f cpu = 4 mhz 2.5 4.5 (2) ma f cpu = 8 mhz 5.0 7.5 supply current in wait mode (3) f cpu = 4 mhz 0.85 2.0 (2) f cpu = 8 mhz 1.2 3.5 supply current in slow mode (4) f cpu /32 = 250 khz 600 950 a supply current in slow-wait mode (5) f cpu /32 = 250 khz 450 750 supply current in awufh mode (6)(7) 45 100 (2) supply current in active halt mode 100 250 supply current in halt mode (8) t a = 85 c 0.5 3.0 t a = 125 c 0.5 5.0 supply current in run mode (1) v dd =3v f cpu = 4 mhz 1.30 2.0 (2) ma supply current in wait mode (3) f cpu = 4 mhz 0.36 0.5 (2) supply current in slow mode (4) f cpu /32 = 250 khz 300 400 (2) a supply current in slow-wait mode (5) f cpu /32 = 250 khz 250 350 (2) supply current in awufh mode (6)(7) 20 50 (2) supply current in active halt mode 90 150 (2) supply current in halt mode (8) t a = 85 c 0.25 2.5 (2) t a = 125 c 0.25 4.5 (2) 1. cpu running with memory access , all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 2. data based on characterization, not tested in production. 3. all i/o pins in input mode with a static value at vdd or vss (no load), all peripherals in reset state; clock input (clkin) driven by external sq uare wave, lvd disabled. 4. slow mode selected with fcpu based on fosc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 5. slow-wait mode selected with fcpu bas ed on fosc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 6. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 7. this consumption refers to the halt period only an d not the associated run period which is software dependent. 8. all i/o pins in output mode with a static value at vss ( no load), lvd disabled. data bas ed on characterization results, tested in production at v dd max and f cpu max.
electrical characteristics st7liteu05 st7liteu09 102/139 13.4.2 internal rc oscillator supply characteristics table 55: internal rc oscillator supply characterisctics symbol parameter conditions min typ max (1) 1. data based on characterization results, not tested in production. unit i dd supply current in run mode (2) 2. cpu running with memory access, all i/o pi ns in input mode with a static value at vdd or vss (no load), all peripherals in reset state; cpu clock provided by the internal rc, lvd disabled. rc oscillator calibrated at 5.0v t a =25 c, int rc = 4 mhz 3.2 5.5 ma t a =25 c, int rc = 8 mhz 5.7 8.5 t a =25 c, awu rc 0.13 0.2 supply current in wait mode (3) 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in rese t state; cpu clock provided by the internal rc, lvd disabled. t a =25 c, int rc = 4 mhz 1.5 3.0 t a =25 c, int rc = 8 mhz 1.9 4.5 supply current in slow mode (4) 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; cpu cloc k provided by the internal rc, lvd disabled. t a =25 c, int rc/32 = 250 khz 1.3 2.0 supply current in slow-wait mode (5) 5. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pi ns in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; cpu clock provided by the internal rc, lvd disabled. t a =25 c, int rc/32 = 250 khz 1.1 1.8 supply current in active-halt mode 0.8 1.25 i dd supply current in run mode (2) rc oscillator calibrated at 3.3v t a =25 c, int rc = 4 mhz 2.0 3.0 ma t a =25 c, int rc = 2 mhz 1.3 2.0 t a =25 c, awu rc 0.1 0.18 supply current in wait mode (3) t a =25 c, int rc = 4 mhz 1.0 1.6 t a =25 c, int rc = 2 mhz 0.9 1.5 supply current in slow mode (4) t a =25 c, int rc/32 = 250 khz 0.95 1.5 supply current in slow-wait mode (5) t a =25 c, int rc/32 = 250 khz 0.85 1.4 supply current in active-halt mode 0.8 1.3
st7liteu05 st7liteu09 elec trical characteristics 103/139 figure 46. typical i dd in run mode vs. internal clock frequency and v dd figure 47. typical i dd in wfi mode vs. internal clock frequency and v dd figure 48. typical i dd in slow, slow-wait and active-halt mode vs v dd & int rc = 8 mhz idd run mode @amb vs int clock freq 0.00 1.00 2.00 3.00 4.00 5.00 6.00 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 vdd [v] idd run [ma] rc 8 m hz rc 4 m hz rc 2 m hz awu idd wfi mode @amb vs int rc freq 0.700 0.900 1.100 1.300 1.500 1.700 1.900 2.100 2.300 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 vdd [v] idd run [ma] 8 mhz 4 mhz 2 mhz idd slow , slow w ait & acthalt mode, int rc 8mhz@am b 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 vdd [v] idd run [ma] slow slowwait acthlt
electrical characteristics st7liteu05 st7liteu09 104/139 figure 49. idd vs temp @v dd 5 v & int rc = 8 mhz figure 50. idd vs temp @v dd 5 v & int rc = 4 mhz figure 51. idd vs temp @v dd 5v & int rc = 2 mhz 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -45 25 90 130 temp [c] idd [ma] run wfi slow slowwait acthlt 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -45 25 90 130 temp [c] idd [ma] run wfi 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -45 25 90 130 temp [c] idd [ma] run wfi
st7liteu05 st7liteu09 elec trical characteristics 105/139 13.4.3 on-chip peripherals 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . table 56. on-chip peripheral characteristics symbol parameter conditions typ (1) 1. not tested in production, guar anteed by characterization. unit i dd(at) 12-bit auto-reload ti mer supply current (2) 2. data based on a differential i dd measurement between reset configuration (timer stopped) and the timer running in pwm mode at f cpu = 8 mhz. f cpu = 4 mhz v dd = 3.0 v 15 a f cpu = 8 mhz v dd = 5.0 v 30 i dd(adc) adc supply current when converting (3) 3. data based on a differential i dd measurement between reset configuration and c ontinuous a/d conversions with amplifier off. f adc = 2 mhz v dd = 3.0 v 450 f adc = 4 mhz v dd = 5.0 v 750 table 57. general timings symbol parameter (1) 1. data based on characterization. not tested in production. conditions min typ (2) 2. data based on typical application software. max unit t c(inst) instruction cycle time f cpu = 8 mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time (3) t v(it) = t c(inst) + 10 3. time measured between interrupt event and interrupt vector fetch. t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. f cpu = 8 mhz 10 22 t cpu 1.25 2.75 s table 58. auto-wakeup rc oscillator parameter conditions min typ max unit supply voltage range 2.4 5.0 5.5 v operating temperature range -40 25 125 c current consumption (1) 1. data guaranteed by design. without prescaler 2.0 8.0 14.0 a consumption (1) awu rc switched off 0 a output frequency (f awu_rc ) (1) 20 33 60 khz
electrical characteristics st7liteu05 st7liteu09 106/139 13.6 memory characteristics t a = -40 c to 125 c, unless otherwise specified table 59. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers ( only in halt mode). guaranteed by c onstruction, not tested in production. halt mode (or reset) 1.6 v table 60. flash program memory symbol parameter conditions min typ max unit v dd operating voltage for flash write/erase 2.4 5.5 v t prog programming time for 1~32 bytes (1) 1. up to 32 bytes can be programmed at a time. t a = ? 40 to +125 c 5 10 ms programming time for 2 kbytes t a = +25 c 0.32 0.64 s t ret data retention (2) 2. data based on reliability test results and monitored in production. t a = +55 c (3) 3. the data retention time increases when t a decreases. 20 years n rw write erase cycles t a = +25 c 10k cycles i dd supply current (4) 4. guaranteed by design. not tested in production. read / write / erase modes f cpu = 8 mhz, v dd = 5.5 v 2.6 ma no read/no write mode 100 a power down mode / halt 00.1 a table 61. eeprom data memory symbol parameter cond itions min typ max unit v dd operating voltage for eeprom write/erase refer to operating range of v dd with t a, section 13.3.1: general operating conditions on page 97 2.4 5.5 v t prog programming time for 1~32 bytes t a = ? 40 to +125 c 5 10 ms t ret data retention (1) 1. data based on reliability test results and monitored in production. t a = +55 c (2) 2. the data retention time increases when t a decreases. 20 years n rw write erase cycles t a = +25 c 300k cycles
st7liteu05 st7liteu09 elec trical characteristics 107/139 13.7 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 13.7.1 functional ems (elect ro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015).
electrical characteristics st7liteu05 st7liteu09 108/139 13.7.2 emi (electromagnetic interference) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the board and the loading of each pin. 13.7.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: human body model. this test conforms to the jesd22-a114a/a115a standard. table 62. ems test results symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8 mhz, so8 package, conforms to iec 1000-4-2 3b v fftb fast transient voltage burst limits to be applied through 100 pf on v ss and v dd pins to induce a functional disturbance v dd = 5 v, t a = +25 c, f osc = 8 mhz, so8 package, conforms to iec 1000-4-4 4a table 63. emi emissions symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit -/8 mhz s emi peak level v dd = 5 v, t a = +25 c, so8 package, conforming to sae j 1752/3 0.1 mhz to 30 mhz 20 db v 30 mhz to 130 mhz 20 130 mhz to 1 ghz 13 sae emi level 2.5 -
st7liteu05 st7liteu09 elec trical characteristics 109/139 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance. a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 64. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electro-static discharge voltage (human body model) 4000 v v esd(cdm) electro-static discharge voltage (charge device model) t a = +25 c 500 v table 65. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a = +125 c a table 66. general characteristics symbol parameter conditions min typ max unit v il input low level voltage -40 c to 125 c 0.3xv dd v v ih input high level voltage 0.7 x v dd v hys schmitt trigger voltage hysteresis (1) 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption induced by each floating input pin (2) floating input mode 400 r pu weak pull-up equivalent resistor (3) (4) v in = v ss v dd = 5 v 70 110 200 k v dd = 3 v 200 (1)
electrical characteristics st7liteu05 st7liteu09 110/139 figure 52. two typical applications with unused i/o pin caution: during normal operation the iccclk pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset note: i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. figure 53. typical i pu vs. v dd with v in =v ss c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time (1) c l = 50 pf between 10% and 90% 25 ns t r(io)out output low to high level rise time (1) 25 t w(it)in external interrupt pulse time (5) 1t cpu 1. data based on characterization results, not tested in production. 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 57 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristics, not tested in pr oduction. this value depends on v dd and temperature values. 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteri stics described in figure 54 ). 4. r pu not applicable on pa3 because it is multiplexed on reset pin 5. to generate an external interrupt, a mini mum pulse width has to be applied on an i/o port pin configured as an external interrupt source. table 66. general characteristics (continued) symbol parameter conditions min typ max unit 10k unused i/o port st7xxx 10k unused i/o port st7xxx v dd 0 10 20 30 40 50 60 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 vdd [v] ipu [ua] -45c 25c 90c 130c
st7liteu05 st7liteu09 elec trical characteristics 111/139 figure 54. typical r pu vs. v dd with v in =v ss 13.8.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. 0 50 100 150 200 250 300 350 400 450 500 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 vdd [v] ipu [ua] -45c 25c 90c 130c table 67. output driving current characteristics symbol parameter con ditions min max unit v ol (1) output low level voltage for pa3/reset standard i/o pin (see figure 57 ) v dd =5 v i io = +5 ma,t a 125 c 1200 mv i io = +2 ma,t a 125 c 400 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 60 ) i io = +20 ma, t a 125 c 1300 i io = +8 ma,t a 125 c 750 v oh (2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 63 ) i io = -5 ma,t a 125 c v dd -1500 i io = -2 ma,t a 125 c v dd -800 v ol (1)(3) output low level voltage for pa3/reset standard i/o pin (see figure 56 ) v dd =3 v i io = +2 ma,t a 125 c 500 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 59 ) i io = +2 ma,t a 125 c 180 i io = +8 ma,t a 125 c 600 v oh (2)(3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 62 ) i io = -2 ma,t a 125 c v dd -800 v ol (1)(3) output low level voltage for pa3/reset standard i/o pin (see figure 55 ) v dd =2.4 v i io = +2 ma,t a 125 c 700 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 58 ) i io = +2 ma,t a 125 c 200 i io =+8 ma,t a 125 c 800 v oh (2)(3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 61 ) i io =-2 ma,t a 125 c v dd -900 1. the i io current sunk must always respect the absolute maximum rating specified in table 46 on page 96 and the sum of i io (i/o ports and control pins) must not exceed i vss .
electrical characteristics st7liteu05 st7liteu09 112/139 figure 55. typical v ol at v dd = 2.4 v (standard pins) figure 56. typical v ol at v dd = 3 v (standard pins) figure 57. typical v ol at v dd = 5 v (standard pins) 2. the i io current sourced must always respect th e absolute maximum rating specified in table 46 on page 96 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins do not have v oh . 3. not tested in production, based on characterization results. 0 200 400 600 800 1000 1200 1400 024 iol [ma] vol [mv] -45c 25c 90c 130c 0 200 400 600 800 1000 1200 1400 02468 iol [ma] vol [mv] -45c 25c 90c 130c 0 200 400 600 800 1000 1200 02468 iol [ma] vol [mv] -45c 25c 90c 130c
st7liteu05 st7liteu09 elec trical characteristics 113/139 figure 58. typical v ol at v dd = 2.4 v (hs pins) figure 59. typical v ol at v dd = 3 v (hs pins) figure 60. typical v ol at v dd = 5 v (hs pins) 0 200 400 600 800 1000 1200 02 46810121416 iol [ma] vol [mv] -45c 25c 90c 130c 0 200 400 600 800 1000 1200 1400 02468101214161820 iol [ma] vol [mv] -45c 25c 90c 130c 0 100 200 300 400 500 600 700 800 02468101214161820 iol [ma] vol [mv] -45c 25c 90c 130c
electrical characteristics st7liteu05 st7liteu09 114/139 figure 61. typical v dd -v oh at v dd = 2.4 v (hs pins) figure 62. typical v dd -v oh at v dd = 3 v (hs pins) figure 63. typical v dd -v oh at v dd = 5 v (hs pins) 0 200 400 600 800 1000 1200 1400 1600 1800 024681012 iol [ma] vdd-voh [mv] -45c 25c 90c 130c 0 200 400 600 800 1000 1200 1400 1600 1800 0 2 4 6 8 1012141618 iol [ma] vdd-voh [mv] -45c 25c 90c 130c 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 101214161820 iol [ma] vdd-voh [mv] -45c 25c 90c 130c
st7liteu05 st7liteu09 elec trical characteristics 115/139 figure 64. typical v ol vs. v dd (hs pins) figure 65. typical v dd -v oh vs. v dd (hs pins) 40 50 60 70 80 90 100 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 vdd [v] vol [mv] vs vdd at iload=2ma -45c 25c 90c 130c 100 150 200 250 300 350 400 450 500 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 vdd [v] vol [mv] vs vdd at iload=8ma -45c 25c 90c 130c 200 300 400 500 600 700 800 900 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 vdd [v] vol [mv] vs vdd at iload=12ma -45c 25c 90c 130c 40 60 80 100 120 140 160 180 200 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 vdd [v] vdd-voh [mv] vs vdd @ iload=2 ma -45c 25c 90c 130c 100 200 300 400 500 600 700 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 vdd [v] vdd-voh [mv] vs vdd @ iload=6 ma -45c 25c 90c 130c
electrical characteristics st7liteu05 st7liteu09 116/139 13.9 control pin characteristics 13.9.1 asynchronous reset pin t a = -40 c to 125 c, unless otherwise specified table 68. asynchronous reset pin characteristics symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis (1) 2v v ol output low level voltage (2) v dd = 5 v i io = +2 ma 400 mv r on pull-up equivalent resistor (3) v in = v ss v dd = 5 v 30 50 70 k v dd = 3 v 90 (1) t w(rstl)out generated reset pulse duration internal reset sources 90 (1) s t h(rstl)in external reset pulse hold time (4) 20 s t g(rstl)in filtered glitch duration 200 ns 1. data based on characterization results, not tested in production. 2. the i io current sunk must always respect t he absolute maximum rating specified in table 46 on page 96 and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resist ive transistor. specified for voltages on reset pin between v ilmax and v dd 4. to guarantee the reset of the device, a minimum pulse has to be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored.
st7liteu05 st7liteu09 elec trical characteristics 117/139 figure 66. reset pin protection when lvd is enabled 1. please refer to section 12.2.1: illegal opcode reset on page 92 for more details on illegal opcode reset conditions the reset network protects the device against parasitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 116 . otherwise the reset will not be taken into account interna lly. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in table 46 on page 96 . when the lvd is enabled, it is recommended not to connect a pull-up resistor or capacitor. a 10 nf pull-down capacitor is required to filter noise on the reset line. in case a capacitive power supply is used, it is recommended to connect a 1 m pull-down resistor to the reset pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). tips when using the lvd check that all recommendations related to iccclk and reset circuit have been applied (see caution in table 2 on page 15 and notes above). check that the power supply is properly decoupled (100 nf + 10 f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100 nf + 1 m pull-down on the reset pin. the capacitors connected on the reset pin and also the power supply are key to avoid any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. othe rwise: replace 10 nf pull-down on the reset pin with a 5 f to 20 f capacitor.? 0.01 f st7xxx pulse generator filter r on v dd internal reset reset external required 1m optional watchdog lvd reset illegal opcode 1)
electrical characteristics st7liteu05 st7liteu09 118/139 figure 67. reset pin protection when lvd is disabled 1. please refer to section 12.2.1 on page 92 for more details on ill egal opcode reset conditions. 2. the reset network protects t he device against par asitic resets. the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 13.9.1 on page 116 . otherwise the reset will not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in table 46 on page 96 . 13.10 10-bit adc characteristics subject to general operating condition for v dd , f osc , and t a unless otherwise specified. 0.01 f external reset circuit user required st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode 1) table 69. adc characteristics symbol parameter conditions min typ (1) max unit f adc adc clock frequency (2) 4mhz v ain conversion voltage range v ss v dd v r ain external input resistor v dd = 5 v, f adc = 4 mhz 8k (3) v dd = 3.3 v, f adc = 4 mhz 7k (3) 2.7 v v dd 5.5 v, f adc = 2 mhz 10k (3) 2.4 v v dd 2.7 v, f adc = 1 mhz 20k (3) c adc internal sample and hold capacitor 3pf t stab stabilization time after adc enable f cpu = 8 mhz, f adc = 4 mhz 0 (4) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc 1. unless otherwise specified, typical data are based on t a =25 c and v dd -v ss = 5 v. they are given only as design guidelines and are not tested. 2. the maximum adc clock frequency allowed within v dd = 2.4 v to 2.7 v operating range is 1 mhz.
st7liteu05 st7liteu09 elec trical characteristics 119/139 figure 68. typical application with adc 3. any added external serial resistor wi ll downgrade the adc accuracy (especially for resistance greater than the maximum value). data guaranteed by design, not tested in production. 4. the stabilization time of the a/d converter is masked by the first t load . the first conversion afte r the enable is then always valid. table 70. adc accuracy with v dd = 3.3 v to 5.5 v symbol (1) 1. data based on characterization results over the whole temperature range. parameter conditions typ max unit |e t | total unadjusted error f cpu = 8 mhz, f adc =4 mhz (1) 2.0 5.0 lsb |e o | offset error 0.9 2.5 |e g | gain error 1.0 1.5 |e d | differential linearity error 1.2 3.5 |e l | integral linearity error 1.1 4.5 table 71. adc accuracy with v dd = 2.7 v to 3.3 v symbol (1) 1. data based on characterization results over the whole temperature range. parameter conditions typ max unit |e t | total unadjusted error f cpu = 4 mhz, f adc = 2 mhz (1) 1.9 3.0 lsb |e o | offset error 0.9 1.5 |e g | gain error 0.8 1.4 |e d | differential linearity error 1.4 2.5 |e l | integral linearity error 1.1 2.5 ainx st7liteu0x v dd i l 1 a v t 0.6 v v t 0.6 v c adc v ain r ain 10-bit a/d conversion
electrical characteristics st7liteu05 st7liteu09 120/139 figure 69. adc accura cy characteristics 1. example of an actual transfer curve 2. the ideal transfer curve 3. end point correlation line 4. e t =total unadjusted error: maximu m deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual table 72. adc accuracy with v dd = 2.4 v to 2.7 v symbol (1) 1. data based on characterization results at ambient temperature and above. parameter conditions typ max unit |e t | total unadjusted error f cpu = 2 mhz, f adc =1 mhz (1) 2.5 3.5 lsb |e o | offset error 1.1 1.5 |e g | gain error 0.5 1.5 |e d | differential linearity error 1.1 2.5 |e l | integral linearity error 1.2 2.5 e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss
st7liteu05 st7liteu09 package characteristics 121/139 14 package characteristics in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack? specifications are available at: www.st.com. 14.1 package mechanical data figure 70. 8-lead very thin fine pitch dual flat no-lead package, package outline a1 a3 (d/2 x e/2) d e a b e (d/2 x e/2) l e2 top view side view bottom view d2 index area index area
package characteristics st7liteu05 st7liteu09 122/139 table 73. 8-lead very thin fine pitch dual flat no-lead package, mechanical data figure 71. 8-pin plastic small outline package - 150-mil width, package outline dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.00 0.02 0.05 0.0008 0.0020 a3 0.20 0.0079 b 0.25 0.30 0.35 0.0098 0.0118 0.0138 d 4.50 0.1772 d2 3.50 3.65 3.75 0.1378 0.1437 0.1476 e 3.50 0.1378 e2 1.96 2.11 2.21 0.0772 0.0831 0.0870 e 0.80 0.0315 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 number of pins n8 d b a1 a h x 45 a2 h e e l c
st7liteu05 st7liteu09 package characteristics 123/139 table 74. 8-pin plastic small outline package - 150-mil width, mechanical data figure 72. 8-pin plastic dual in-line outline package - 300-mil width, package outline dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 1.35 1.75 0.0531 0.0689 a1 0.10 0.25 0.0039 0.0098 a2 1.10 1.65 0.0433 0.0650 b 0.33 0.51 0.0130 0.0201 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 0.1890 0.1969 e 3.80 4.00 0.1496 0.1575 e 1.27 0.0500 h 5.80 6.20 0.2283 0.2441 h 0.25 0.50 0.0098 0.0197 0 8 0 8 l 0.40 1.27 0.0157 0.0500 number of pins n8 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
package characteristics st7liteu05 st7liteu09 124/139 table 75. 8-pin plastic dual in-line outline package, 300-mil width, mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a5.330.2098 a1 0.38 0.0150 a2 3.3 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.0220 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.2 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.3650 0.3551 0.4000 e 7.87 7.62 8.26 0.3098 0.3000 0.3252 e1 6.35 6.1 7.11 0.2500 0.2402 0.2799 e 2.54 - - 0.1000 ea 7.62 - - 0.3000 eb 10.92 0.4299 l 3.3 2.92 3.81 0.1299 0.1150 0.1500
st7liteu05 st7liteu09 package characteristics 125/139 figure 73. 16-pin plastic dual in-line package, 300-mil width, package outline table 76. 16-pin plastic dual in-line package, 300-mil width, mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 5.33 0.2098 a1 0.38 0.0150 a2 2.92 3.30 4.95 0.1150 0.1299 0.1949 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 b2 1.14 1.52 1.78 0.0449 0.0598 0.0701 b3 0.76 0.99 1.14 0.0299 0.0390 0.0449 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 d 18.67 19.18 19.69 0.7350 0.7551 0.7752 d1 0.13 0.0051 e 2.54 0.1000 e 7.62 7.87 8.26 0.3000 0.3098 0.3252 e1 6.10 6.35 7.11 0.2402 0.2500 0.2799 l 2.92 3.30 3.81 0.1150 0.1299 0.1500 eb 10.92 0.4299 number of pins n16 c e e1 eb l a a2 a1 e b b2 b3 d
package characteristics st7liteu05 st7liteu09 126/139 table 77. package characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) dip8 82 c/w so8 130 dfn8 (on 4-layer pcb) dfn8 (on 2-layer pcb) 50 106 t jmax maximum junction temperature (1) 1. the maximum chip-junction temperature is based on technology characteristics. 150 c p dmax power dissipation (2) 2. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int +p port where p int is the chip internal power (i dd x v dd ) and p port is the port power dissipati on depending on the ports used in the application. dip8 300 mw so8 180 dfn8 (on 4-layer pcb) 500 dfn8 (on 2-layer pcb) 250
st7liteu05 st7liteu09 device configuration and ordering information 127/139 15 device configuration and ordering information each device is available for production in user programmable versions (flash) as well as in factory coded versions (fastrom). st7pliteu05 and st7pliteu09 devices are factory advanced service technique rom (fastrom) versions of st7liteu05 and st7liteu09 devices : they are factory- programmed xflash devices. st7fliteu05 and st7fliteu09 xflash devices are xflash versions of st7liteu05 and st7liteu09 devices. they are shipped to customers with a default program memory content (ffh). the fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the fastrom devices are factory-configured. 15.1 option bytes the two option bytes allow the hardware configuration of the microcontroller to be selected. the option bytes can be accessed only in programming mode (for example using a standard st7 programming tool). 15.1.1 option byte 1 bits 7:6 = cksel[1:0] startup clock selection. this bit is used to select the startup frequency. by default, the internal rc is selected. bit 5 = reserved, must always be 1. bit 4 = reserved, must always be 0. bits 3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a selected threshold as shown in ta bl e 7 9 . table 79. lvd threshold configuration table 78. startup clock selection configuration cksel1 cksel0 internal rc as startup clock 0 0 awu rc as a startup clock 0 1 reserved 1 0 external clock on pin pa5 1 1 configuration lvd1 lvd0 lv d o f f 1 1 highest voltage threshold 1 0 medium voltage threshold 0 1 lowest voltage threshold 0 0
device configuration and ordering information st7liteu05 st7liteu09 128/139 bit 1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) bit 0 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode 15.1.2 option byte 0 bits 7:4 = reserved, must always be set. bits 3:2 = sec[1:0] sector 0 size definition this option bit indicates the size of sector 0 according to the following table. bit 1 = fmp_r readout protection readout protection, when selected provides a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is se lected will cause the whole memory to be erased first, and the device can be reprogrammed. refer to section 4.5 and the st7 flash programming reference manual for more details. 0: readout protection off 1: readout protection on bit 0 = fmp_w flash write protection this option indicates if the flash program memory is write protected. 0: write protection off 1: write protection on warning: when this option is selected, the program memory (and the option bit itself) can never be erased or programmed again. table 80. sector 0 size selection sector 0 size sec0 sec1 0.5k 00 1k 01 2k 1-
st7liteu05 st7liteu09 device configuration and ordering information 129/139 15.2 ordering information customer code is made up of the fastrom contents and the list of the selected options (if any). the fastrom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide de tailed information on contractual points. option byte 0 70 option byte 1 70 reserved sec 1 sec 0 fmpr fmpw cksel 1 cksel 0 reserved lvd1 lvd0 wdg sw wdg halt default value 1111 0 0 0 0 0 0 10 1 1 1 1
device configuration and ordering information st7liteu05 st7liteu09 130/139 figure 74. st7liteu0 ordering information scheme 1. dip16 for development or tool prototyping pur poses only, not orderable in production quantities. st7 f liteu05 u 0 b 6 tr family st7 microcontroller family memory size 0 = 2k package b = dip 1) m = so u = dfn example: no. of pins u = 8 sub-family liteu05 liteu09 temperature range 6 = -40 c to 85 c 3 = -40 c to 125 c for a list of available options (e.g. memory size, package) and orderab le part numbers or for further information on any aspect of this device, please contact the st sales office nearest to you. shipping option tr = tape & reel (so8 or dfn8) blank = tube (dip8 or so8) or tray (dfn8) version f= flash p= fastrom
st7liteu05 st7liteu09 device configuration and ordering information 131/139 st7liteu0 fastrom microcontroller option list (last update: october 2008) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference fastrom code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *fastrom code name is assi gned by stmicroelectronics. fastrom code must be sent in .s19 form at. .hex extension cannot be processed. package (check only one option) : pdip8: so8: dfn8: conditioning (check only one option) : dip package: [ ] tube so package: [ ] tape & reel [ ] tube dfn package: [ ] tape & reel [ ] tray (st7liteu09 only) special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ " authorized characters are letters, digi ts, '.', '-', '/' and spaces only. maximum character count: pdip8 / so8 / dfn8 (8 char. max) : _ _ _ _ _ _ _ _ temperature range: [ ] -40c to +85c [ ] -40c to +125c clock source selection: [ ] external clock [ ] awu rc oscillator [ ] internal rc oscillator sector 0 size: [ ] 0.5k [ ] 1k [ ] 2k readout protection: [ ] disabled [ ] enabled flash write protection [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] highest threshold [ ] medium threshold [ ] lowest threshold watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt: [ ] disabled [ ] enabled comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . important note: not all configurations are available. see section 15.1 on page 127 for authorized option byte combinations. please download the latest version of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list
device configuration and ordering information st7liteu05 st7liteu09 132/139 15.3 development tools development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 15.3.1 starter kits st offers complete, affordable starter kits . starter kits are complete hardware/software tool packages that include features and samples to help you quickly start developing your application. 15.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seamlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c comp iler is available in a free version that outputs up to 16 kbytes of code. the range of hardware tools includes full-featured st7-emu3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 15.3.3 programming tools during the development cycle, the st7-emu3 series emulators and the rlink provide in- circuit programming capability fo r programming the flash microc ontroller on your application board. st also provides a low-cost dedicated in-circuit programmer, the st7-stick , as well as st7 socket boards which provide all the sockets requ ired for programming any of the devices in a specific st7 sub-family on a platform that can be used with any tool with in- circuit programming capability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. 15.3.4 order codes for developm ent and programming tools ta bl e 8 1 below lists the ordering codes for the st7liteu0x development and programming tools. for additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu.
st7liteu05 st7liteu09 device configuration and ordering information 133/139 table 81. development tool order codes for the st7liteu0x family supported products in-circuit debugger, rlink series (1) 1. available from st or from raisonance, www.raisonance.com emulator programming tool starter kit without demo board starter kit with demo board in-circuit programmer st socket boards and epbs st7fliteu05 st7fliteu09 stx-rlink (2) 2. usb connection to pc st7flite-sk/rais (2) st7mdt10-emu3 (3) 3. includes connection kit for dip16/so16 only. see ?how to orde r an emu or dvp? in st product and tool selection guide for connection kit ordering information stx-rlink st7-stick (4)(5) 4. add suffix /eu, /uk or /us for the power supply for your region 5. parallel port connection to pc st7sb10-su0 (4)
device configuration and ordering information st7liteu05 st7liteu09 134/139 15.4 st7 application notes table 82. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative input voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication be tween st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad
st7liteu05 st7liteu09 device configuration and ordering information 135/139 an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations us ing st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art an1947 st7mc pmac sine wave mo tor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can c ontrollers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite 1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption table 82. st7 application notes (continued) identification description
device configuration and ordering information st7liteu05 st7liteu09 136/139 an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscillator an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an1039 st7 math utility routines an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ programming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc table 82. st7 application notes (continued) identification description
st7liteu05 st7liteu09 device configuration and ordering information 137/139 an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma- delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection duri ng pwm on time by st7mc table 82. st7 application notes (continued) identification description
revision history st7liteu05 st7liteu09 138/139 16 revision history table 83. document revision history date revision main changes 19-jan-07 0.1 initial release 03-may-07 1 added note 1 to table 2 on page 15 modified ?a/d conversion? on page 83 and added ?changing the conversion channel? on page 83 updated section 13.3.2 on page 98 , section 13.3.3 on page 98 , section 13.8.1 on page 109 , and section 13.3.2 on page 98 modified eoc bit description in section 11.3.6 on page 84 updated ?internal rc oscillator calibrated at 5.0 v? on page 99 and ?internal rc oscillator calibrated at 3.3 v? on page 100 supply current curved updated in section 13.4 on page 101 updated section 13.4.1 on page 101 added one r ain value and modified note 3 in section 13.10 on page 118 removed references to st7liteu02 part numbers modified reset configuration for pin n6 in table 2 on page 15 modified figure 14 on page 34 (added avdthcr) added table 61 on page 106 modified table 81 on page 133 : added note 4 for st7mdt10-emu3, removed references to dvp3 and modified starter kit part number. modified table 60 on page 106 (n rw ) modified ?electrostatic discharge (esd)? on page 108 modified temperature conditions for lu in section on page 109 adc accuracy maximum values inserted into tables in ?10-bit adc characteristics? on page 118 ipu and rpu graphs updated, figure 53 and figure 54 on page 111 supply characteristics graphs updated, section 13.4 on page 101 rc oscillator consumption data table inserted, section 13.4.2 on page 102 internal rc oscillator data tables updated, ?internal rc oscillator calibrated at 5.0 v? on page 99, ?internal rc oscill ator calibrated at 5.0 v? on page 99 consumption values for halt mode inserted, section 13.4 on page 101 31-oct-08 2 format of the document changed status of the document modified ( datasheet instead of preliminary data) one paragraph added below figure 66 on page 117 section 13.7.3: absolute maximum rati ngs (electrical sensitivity) on page 108 modified section 14.1: package mechanical data on page 121 modified soldering information section removed section 15: device configuration and ordering information on page 127 updated
st7liteu05 st7liteu09 139/139 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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